204 lines
5.3 KiB
C
204 lines
5.3 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* Author: Sathish Kuttan <sathish.k.kuttan@intel.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Intel GNA device driver
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*
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* Device driver implementation for Intel's
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* Gaussian Mixture Model and Neural Network Accelerator (GNA)
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*/
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#ifndef __INTEL_GNA__
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#define __INTEL_GNA__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* number of requests that could be pending in driver */
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#define GNA_REQUEST_QUEUE_LEN CONFIG_INTEL_GNA_MAX_PENDING_REQUESTS
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#define GNA_MAX_NUM_MODELS CONFIG_INTEL_GNA_MAX_MODELS
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/* values must match config values in Kconfig.intel_gna */
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#define GNA_POWER_MODE_ALWAYS_ON 0
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#define GNA_POWER_MODE_CLOCK_GATED 1
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#define GNA_POWER_MODE_POWER_GATED 2
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#define GNA_POWER_MODE_ALWAYS_OFF 3
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#define INTEL_GNA_BASE_ADDR 0x0000E800
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#define INTEL_GNA_IRQ_ID 0x00000506
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#define INTEL_GNA_IRQ_PRIORITY 3
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#define GNA_STS_INTR_PENDING BIT(31)
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#define GNA_STS_SATURATION_OCCURRED BIT(17)
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#define GNA_STS_BUFFER_FULL BIT(16)
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#define GNA_STS_ERROR BIT(15)
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#define GNA_STS_PARAM_OOR BIT(8)
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#define GNA_STS_VIRT_ADDR_OOR BIT(7)
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#define GNA_STS_STATS_VALID BIT(3)
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#define GNA_STS_SUSP_PAUSE BIT(2)
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#define GNA_STS_SUSP_BREAKP BIT(1)
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#define GNA_STS_SCORE_COMPL BIT(0)
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#define GNA_CTRL_INTR_DISABLE BIT(31)
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#define GNA_CTRL_PM_IDLE_DISABLE BIT(18)
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#define GNA_CTRL_PM_OVRIDE_CLK_ON BIT(17)
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#define GNA_CTRL_PM_OVRIDE_PWR_ON BIT(16)
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#define GNA_CTRL_STATS_ENABLE_STALL (1 << 12)
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#define GNA_CTRL_STATS_MASK (BIT_MASK(4) << 12)
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#define GNA_CTRL_ERR_INTR_ENABLE (1 << 10)
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#define GNA_CTRL_COMPL_INTR_ENABLE (1 << 8)
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#define GNA_CTRL_OPER_MODEL_XNN (1 << 5)
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#define GNA_CTRL_ABORT_CLEAR (1 << 2)
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#define GNA_CTRL_ACCEL_START (1 << 0)
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#define GNA_CTRL_ACCEL_BUSY GNA_CTRL_ACCEL_START
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#define GNA_CONFIG_DESC_PG_DIR_SIZE 64
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#define GNA_LAYER_DESC_ALIGN (128)
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#define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE
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#define GNA_NUM_PG_TABLE_INDEX_BITS 10
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#define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS)
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#define GNA_PG_SIZE_IN_BITSHIFT 12
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#define GNA_PG_SIZE_IN_BYTES BIT(GNA_PG_SIZE_IN_BITSHIFT)
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#define GNA_SHIFT_RNDUP(value, shift) (((value) + BIT_MASK(shift)) >> (shift))
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#define GNA_NUM_PAGES(bytes) \
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GNA_SHIFT_RNDUP((bytes), GNA_PG_SIZE_IN_BITSHIFT)
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#define GNA_PAGES_TO_BYTES(pages) ((pages) << GNA_PG_SIZE_IN_BITSHIFT)
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#define GNA_MAX_NUM_PAGES GNA_NUM_PAGES(GNA_ADDRESSABLE_MEM_SIZE)
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#define GNA_NUM_PG_TABLES_NEEDED \
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GNA_SHIFT_RNDUP(GNA_MAX_NUM_PAGES, GNA_NUM_PG_TABLE_INDEX_BITS)
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#if GNA_NUM_PG_TABLES_NEEDED > GNA_CONFIG_DESC_PG_DIR_SIZE
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#error GNA_NUM_PG_TABLES_NEEDED exceeds GNA_CONFIG_DESC_PG_DIR_SIZE
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#endif
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#define GNA_GET_BITS(val, b_hi, b_lo) ((((u32_t)(val)) << (31 - (b_hi))) >> \
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(31 - (b_hi) + (b_lo)))
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#define GNA_VA_PG_DIR(virt_addr) GNA_GET_BITS(virt_addr, 27, 22)
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#define GNA_VA_PG_TABLE(virt_addr) GNA_GET_BITS(virt_addr, 21, 12)
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#define GNA_PHYS_ADDR_TO_PAGE(addr) ((u32_t)(addr) >> \
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GNA_PG_SIZE_IN_BITSHIFT)
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#define GNA_PG_DIR_ENTRY(phys_addr) GNA_PHYS_ADDR_TO_PAGE(phys_addr)
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#define GNA_PG_BASE(addr) ((u32_t)(addr) & \
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~BIT_MASK(GNA_PG_SIZE_IN_BITSHIFT))
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#define GNA_PG_OFFSET(addr) ((u32_t)(addr) & \
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BIT_MASK(GNA_PG_SIZE_IN_BITSHIFT))
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#define GNA_PG_TABLE_ENTRY(phys_addr) GNA_PHYS_ADDR_TO_PAGE(phys_addr)
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struct intel_gna_regs {
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u32_t gnasts;
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u32_t gnactrl;
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u32_t gnamctl;
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u32_t gnaptc;
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u32_t gnasc;
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u32_t gnaisi;
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u32_t gnais_low;
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u32_t gnais_high;
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u32_t gnabp_low;
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u32_t gnabp_high;
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u32_t reserved1[2];
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u32_t gnadesbase;
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u32_t gnaibuffs;
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u32_t reserved2[2];
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u32_t ovrcfgctl;
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u32_t reserved3[3];
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u32_t gnaversion;
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};
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struct intel_gna_config_desc {
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u32_t reserved1[64];
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u32_t labase; /* layer array base */
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u16_t lacnt; /* layer array count */
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u16_t reserved2;
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u32_t reserved3[62];
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u32_t vamaxaddr; /* virtual address max address */
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u32_t reserved4[3];
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/* page directory entries */
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u32_t pagedir[GNA_CONFIG_DESC_PG_DIR_SIZE];
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} __packed;
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struct intel_gna_page_table {
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u32_t entry[GNA_NUM_PG_TABLE_ENTRIES];
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} __aligned(GNA_PG_SIZE_IN_BYTES);
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struct intel_gna_layer_desc {
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u32_t gna_words[8];
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u32_t inarrayptr;
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u32_t outarrayactptr;
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u32_t outarraysumptr;
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u32_t outfbarrayactptr;
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u32_t wtfltarrayptr;
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u32_t constarrayptr;
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u32_t actoutputslistptr;
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u32_t actfuncsectdefptr;
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u32_t reserved[16];
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} __packed __aligned(GNA_LAYER_DESC_ALIGN);
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struct intel_gna_config {
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struct gna_config config;
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};
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struct intel_gna_model {
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struct gna_model_info model;
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void *input;
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void *output;
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void *vabase;
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bool registered;
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};
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struct intel_gna_pending_req {
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struct intel_gna_model *model;
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void *output;
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size_t output_len;
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gna_callback callback;
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};
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struct intel_gna_pending_resp {
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struct gna_inference_resp response;
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gna_callback callback;
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};
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enum gna_state {
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GNA_STATE_UNINITIALIZED,
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GNA_STATE_INITIALIZED,
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GNA_STATE_IDLE,
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GNA_STATE_ACTIVE,
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};
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struct intel_gna_data {
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/*
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* gna_cb_work must be the first element in the structure
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* since it will be typecast as intel_gna_data in the work handler
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*/
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struct k_work gna_work;
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volatile struct intel_gna_regs *regs;
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struct k_mem_slab model_slab;
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struct intel_gna_model models[GNA_MAX_NUM_MODELS];
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struct k_msgq request_queue;
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struct intel_gna_pending_req requests[GNA_REQUEST_QUEUE_LEN];
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struct k_msgq response_queue;
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struct intel_gna_pending_resp responses[GNA_REQUEST_QUEUE_LEN];
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enum gna_state state;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INTEL_GNA__ */
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