448 lines
10 KiB
C
448 lines
10 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/clock_control.h>
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#include <kernel.h>
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#include <soc.h>
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#include <errno.h>
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#include <drivers/i2c.h>
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#define SPEED_100KHZ_BUS 0
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#define SPEED_400KHZ_BUS 1
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#define SPEED_1MHZ_BUS 2
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#define WAIT_INTERVAL 5
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/* 250 us */
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#define TIMEOUT 100
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/* 25 us */
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#define MAX_CLK_STRETCHING 5
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struct xec_speed_cfg {
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u32_t bus_clk;
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u32_t data_timing;
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u32_t start_hold_time;
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u32_t config;
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u32_t timeout_scale;
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};
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struct i2c_xec_config {
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u32_t port_sel;
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u32_t base_addr;
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};
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struct i2c_xec_data {
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u32_t pending_stop;
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};
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/* Recommended programming values based on 16MHz
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* i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
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* bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
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* (16MHz/400KHz -2) = 0x0F + 0x17
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* (16MHz/1MHz -2) = 0x05 + 0x09
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*/
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static const struct xec_speed_cfg xec_cfg_params[] = {
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[SPEED_100KHZ_BUS] = {
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.bus_clk = 0x00004F4F,
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.data_timing = 0x0C4D5006,
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.start_hold_time = 0x0000004D,
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.config = 0x01FC01ED,
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.timeout_scale = 0x4B9CC2C7,
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},
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[SPEED_400KHZ_BUS] = {
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.bus_clk = 0x00000F17,
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.data_timing = 0x040A0A06,
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.start_hold_time = 0x0000000A,
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.config = 0x01000050,
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.timeout_scale = 0x159CC2C7,
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},
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[SPEED_1MHZ_BUS] = {
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.bus_clk = 0x00000509,
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.data_timing = 0x04060601,
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.start_hold_time = 0x00000006,
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.config = 0x10000050,
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.timeout_scale = 0x089CC2C7,
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},
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};
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static int xec_spin_yield(int *counter)
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{
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*counter = *counter + 1;
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if (*counter > TIMEOUT) {
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return -ETIMEDOUT;
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}
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if (*counter > MAX_CLK_STRETCHING * 2) {
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k_yield();
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} else {
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k_busy_wait(5);
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}
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return 0;
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}
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static void recover_from_error(u32_t ba)
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{
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STO |
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MCHP_I2C_SMB_CTRL_ACK;
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}
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static int wait_bus_free(u32_t ba)
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{
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int ret;
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int counter = 0;
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while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
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ret = xec_spin_yield(&counter);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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static int wait_completion(u32_t ba)
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{
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int ret;
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int counter = 0;
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/* Wait for transaction to be completed */
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while (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_PIN) {
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ret = xec_spin_yield(&counter);
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if (ret < 0) {
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recover_from_error(ba);
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return ret;
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}
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}
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/* Check if Slave send ACK/NACK */
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_LRB_AD0) {
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recover_from_error(ba);
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return -EIO;
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}
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/* Check for bus error */
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
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recover_from_error(ba);
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return -EBUSY;
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}
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return 0;
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}
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static bool check_lines(u32_t ba)
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{
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return ((!(MCHP_I2C_SMB_BB_CTRL(ba) & MCHP_I2C_SMB_BB_CLKI_RO)) ||
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(!(MCHP_I2C_SMB_BB_CTRL(ba) & MCHP_I2C_SMB_BB_DATI_RO)));
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}
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static int i2c_xec_configure(struct device *dev, u32_t dev_config_raw)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config->config_info);
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u32_t ba = config->base_addr;
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u8_t port_sel = config->port_sel;
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u32_t speed_id;
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u32_t cfg, bb_ctrl;
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u8_t ctrl;
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if (!(dev_config_raw & I2C_MODE_MASTER)) {
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return -ENOTSUP;
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}
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if (dev_config_raw & I2C_ADDR_10_BITS) {
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return -ENOTSUP;
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}
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switch (I2C_SPEED_GET(dev_config_raw)) {
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case I2C_SPEED_STANDARD:
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speed_id = SPEED_100KHZ_BUS;
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break;
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case I2C_SPEED_FAST:
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speed_id = SPEED_400KHZ_BUS;
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break;
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case I2C_SPEED_FAST_PLUS:
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speed_id = SPEED_1MHZ_BUS;
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break;
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default:
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return -EINVAL;
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}
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cfg = MCHP_I2C_SMB_CFG(ba) & MCHP_I2C_SMB_CTRL_MASK;
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bb_ctrl = MCHP_I2C_SMB_BB_CTRL(ba) & MCHP_I2C_SMB_BB_MASK;
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ctrl = MCHP_I2C_SMB_CTRL(ba) & MCHP_I2C_SMB_CTRL_MASK;
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/* Assert RESET and clr others */
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cfg |= MCHP_I2C_SMB_CFG_RESET;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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/* Enable bit-bang mode, do not enable SMBus HW timeouts */
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bb_ctrl |= MCHP_I2C_SMB_BB_EN;
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bb_ctrl |= MCHP_I2C_SMB_BB_SCL_DIR_OUT;
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bb_ctrl |= MCHP_I2C_SMB_BB_SDA_DIR_OUT;
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bb_ctrl |= (MCHP_I2C_SMB_BB_CL | MCHP_I2C_SMB_BB_DAT);
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MCHP_I2C_SMB_BB_CTRL(ba) = bb_ctrl;
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/* Bus reset */
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cfg &= ~MCHP_I2C_SMB_CFG_RESET;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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/* Assert PIN bit, ESO = 0 and disables Interrupts (ENI) */
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ctrl = MCHP_I2C_SMB_CTRL_PIN;
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MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
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/* Port selection */
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cfg |= (port_sel & MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
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MCHP_I2C_SMB_CFG(ba) = cfg;
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/* Enable controller and I2C filters*/
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cfg |= (MCHP_I2C_SMB_CFG_ENAB | MCHP_I2C_SMB_CFG_FEN);
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MCHP_I2C_SMB_CFG(ba) = cfg;
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/* Set own address */
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MCHP_I2C_SMB_OWN_ADDR(ba) = 0x7F;
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/* Configure speed */
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MCHP_I2C_SMB_BUS_CLK(ba) = xec_cfg_params[speed_id].bus_clk;
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MCHP_I2C_SMB_DATA_TM(ba) = xec_cfg_params[speed_id].data_timing;
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MCHP_I2C_SMB_RSHT(ba) = xec_cfg_params[speed_id].start_hold_time;
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MCHP_I2C_SMB_TMTSC(ba) = xec_cfg_params[speed_id].timeout_scale;
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ctrl |= (MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_ENI | MCHP_I2C_SMB_CTRL_ACK);
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MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
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return 0;
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}
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static int i2c_xec_poll_write(struct device *dev, struct i2c_msg msg,
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u16_t addr)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config->config_info);
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->driver_data);
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u32_t ba = config->base_addr;
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int ret;
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if (data->pending_stop == 0) {
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/* Check clock and data lines */
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if (check_lines(ba)) {
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return -EBUSY;
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}
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/* Wait until bus is free */
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ret = wait_bus_free(ba);
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if (ret) {
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return ret;
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}
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/* Send slave address */
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MCHP_I2C_SMB_DATA(ba) = (addr & ~BIT(0));
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/* Send start and ack bits */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
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MCHP_I2C_SMB_CTRL_ACK;
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ret = wait_completion(ba);
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if (ret) {
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return ret;
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}
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}
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/* Send bytes */
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for (int i = 0U; i < msg.len; i++) {
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MCHP_I2C_SMB_DATA(ba) = msg.buf[i];
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ret = wait_completion(ba);
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if (ret) {
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return ret;
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}
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/* Handle stop bit for last byte to write */
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if (i == (msg.len - 1)) {
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if (msg.flags & I2C_MSG_STOP) {
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/* Send stop and ack bits */
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MCHP_I2C_SMB_CTRL_WO(ba) =
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MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STO |
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MCHP_I2C_SMB_CTRL_ACK;
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data->pending_stop = 0;
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} else {
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data->pending_stop = 1;
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}
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}
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}
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return 0;
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}
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static int i2c_xec_poll_read(struct device *dev, struct i2c_msg msg,
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u16_t addr)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config->config_info);
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->driver_data);
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u32_t ba = config->base_addr;
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u8_t byte, ctrl;
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int ret;
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if (!(msg.flags & I2C_MSG_RESTART)) {
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/* Check clock and data lines */
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if (check_lines(ba)) {
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return -EBUSY;
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}
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/* Wait until bus is free */
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ret = wait_bus_free(ba);
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if (ret) {
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return ret;
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}
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}
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/* Send slave address */
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MCHP_I2C_SMB_DATA(ba) = (addr | BIT(0));
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STA | MCHP_I2C_SMB_CTRL_ACK;
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ret = wait_completion(ba);
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if (ret) {
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return ret;
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}
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if (msg.len == 1) {
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/* Send NACK for last transaction */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_STA;
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}
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/* Read dummy byte */
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byte = MCHP_I2C_SMB_DATA(ba);
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ret = wait_completion(ba);
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if (ret) {
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return ret;
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}
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for (int i = 0U; i < msg.len; i++) {
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while (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_PIN) {
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
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return -EBUSY;
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}
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}
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if (i == (msg.len - 1)) {
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if (msg.flags & I2C_MSG_STOP) {
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/* Send stop and ack bits */
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ctrl = (MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STO |
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MCHP_I2C_SMB_CTRL_ACK);
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MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
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data->pending_stop = 0;
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}
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} else if (i == (msg.len - 2)) {
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/* Send NACK for last transaction */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_STA;
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}
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msg.buf[i] = MCHP_I2C_SMB_DATA(ba);
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}
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return 0;
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}
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static int i2c_xec_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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int ret = 0;
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addr <<= 1;
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for (int i = 0U; i < num_msgs; i++) {
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if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
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ret = i2c_xec_poll_write(dev, msgs[i], addr);
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if (ret) {
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return ret;
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}
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} else {
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ret = i2c_xec_poll_read(dev, msgs[i], addr);
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}
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}
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return ret;
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}
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#if defined(CONFIG_I2C_SLAVE)
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static int i2c_xec_slave_register(struct device *dev)
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{
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return -ENOTSUP;
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}
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static int i2c_xec_slave_unregister(struct device *dev)
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{
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return -ENOTSUP;
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}
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#endif
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static int i2c_xec_init(struct device *dev);
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static const struct i2c_driver_api i2c_xec_driver_api = {
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.configure = i2c_xec_configure,
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.transfer = i2c_xec_transfer,
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#if defined(CONFIG_I2C_SLAVE)
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.slave_register = i2c_xec_slave_register,
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.slave_unregister = i2c_xec_slave_unregister,
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#endif
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};
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#ifdef CONFIG_I2C_XEC_0
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static struct i2c_xec_data i2c_xec_data_0;
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static const struct i2c_xec_config i2c_xec_config_0 = {
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.base_addr = DT_INST_0_MICROCHIP_XEC_I2C_BASE_ADDRESS,
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.port_sel = DT_INST_0_MICROCHIP_XEC_I2C_PORT_SEL,
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};
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DEVICE_AND_API_INIT(i2c_xec_0, DT_INST_0_MICROCHIP_XEC_I2C_LABEL,
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&i2c_xec_init, &i2c_xec_data_0, &i2c_xec_config_0,
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
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&i2c_xec_driver_api);
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#endif /* CONFIG_I2C_XEC_0 */
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#ifdef CONFIG_I2C_XEC_1
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static struct i2c_xec_data i2c_xec_data_1;
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static const struct i2c_xec_config i2c_xec_config_1 = {
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.base_addr = DT_INST_1_MICROCHIP_XEC_I2C_BASE_ADDRESS,
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.port_sel = DT_INST_1_MICROCHIP_XEC_I2C_PORT_SEL,
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};
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DEVICE_AND_API_INIT(i2c_xec_1, DT_INST_1_MICROCHIP_XEC_I2C_LABEL,
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&i2c_xec_init, &i2c_xec_data_1, &i2c_xec_config_1,
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
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&i2c_xec_driver_api);
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#endif /* CONFIG_I2C_XEC_1 */
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#ifdef CONFIG_I2C_XEC_2
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static struct i2c_xec_data i2c_xec_data_2;
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static const struct i2c_xec_config i2c_xec_config_2 = {
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.base_addr = DT_INST_2_MICROCHIP_XEC_I2C_BASE_ADDRESS,
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.port_sel = DT_INST_2_MICROCHIP_XEC_I2C_PORT_SEL,
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};
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DEVICE_AND_API_INIT(i2c_xec_2, DT_INST_2_MICROCHIP_XEC_I2C_LABEL,
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&i2c_xec_init, &i2c_xec_data_2, &i2c_xec_config_2,
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
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&i2c_xec_driver_api);
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#endif /* CONFIG_I2C_XEC_2 */
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static int i2c_xec_init(struct device *dev)
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{
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->driver_data);
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data->pending_stop = 0;
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return 0;
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}
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