zephyr/boards/riscv
Peter A. Bigot 73ed1bafd1 boards: hifive1*: fix ticks per second
The HiFive1 boards power up using a 32 KiHz low frequency kernel, so
have a cycle rate of 32768 Hz.  The board definitions have not been
revisited since the Zephyr default for ticks-per-second increased from
100 to 10000.  The timer system on the board does not operate
correctly at 4 cycles per tick, but does at 328 cycles per tick.

To support functional timers while keeping system milliseconds in sync
with clock time set ticks-per-second to 128.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2019-11-27 13:32:16 -05:00
..
hifive1 boards: hifive1*: fix ticks per second 2019-11-27 13:32:16 -05:00
hifive1_revb boards: hifive1*: fix ticks per second 2019-11-27 13:32:16 -05:00
litex_vexriscv kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
m2gl025_miv boards: Clean up references to env variable PROJECT_SOURCE_DIR 2019-09-12 13:16:16 -05:00
qemu_riscv32 dts: jedec,spi-nor: require size property 2019-11-09 15:26:06 +01:00
qemu_riscv64 dts: jedec,spi-nor: require size property 2019-11-09 15:26:06 +01:00
rv32m1_vega boards: rv32m1_vega: Configure led pinmuxes as gpios 2019-11-13 12:05:48 -06:00
index.rst