79 lines
1.2 KiB
C
79 lines
1.2 KiB
C
/*
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Exception/interrupt context helpers for Cortex-R CPUs
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*
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* Exception/interrupt context helpers.
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*/
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#ifndef _ARM_CORTEXR_ISR__H_
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#define _ARM_CORTEXR_ISR__H_
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#include <arch/cpu.h>
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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#include <irq_offload.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef CONFIG_IRQ_OFFLOAD
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extern volatile irq_offload_routine_t offload_routine;
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#endif
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/* Check the CPSR mode bits to see if we are in IRQ or FIQ mode */
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static ALWAYS_INLINE bool arch_is_in_isr(void)
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{
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unsigned int status;
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__asm__ volatile(
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" mrs %0, cpsr"
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: "=r" (status) : : "memory", "cc");
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status &= MODE_MASK;
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return (status == MODE_FIQ) || (status == MODE_IRQ);
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}
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/**
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* @brief Setup system exceptions
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*
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* Enable fault exceptions.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void z_arm_exc_setup(void)
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{
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}
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/**
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* @brief Clear Fault exceptions
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*
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* Clear out exceptions for Mem, Bus, Usage and Hard Faults
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void z_arm_clear_faults(void)
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{
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}
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extern void z_arm_cortex_r_svc(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* _ARM_CORTEXRM_ISR__H_ */
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