525 lines
19 KiB
C
525 lines
19 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMA_IPROC_PAX
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#define DMA_IPROC_PAX
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/* Broadcom PAX-DMA RM register defines */
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#define PAX_DMA_REG_ADDR(_base, _offs) ((_base) + (_offs))
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#define PAX_DMA_RING_ADDR_OFFSET(_ring) (0x10000 * (_ring))
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/* Per-Ring register offsets */
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#define RING_VER 0x000
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#define RING_BD_START_ADDR 0x004
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#define RING_BD_READ_PTR 0x008
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#define RING_BD_WRITE_PTR 0x00c
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#define RING_BD_READ_PTR_DDR_LS 0x010
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#define RING_BD_READ_PTR_DDR_MS 0x014
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#define RING_CMPL_START_ADDR 0x018
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#define RING_CMPL_WRITE_PTR 0x01c
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#define RING_NUM_REQ_RECV_LS 0x020
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#define RING_NUM_REQ_RECV_MS 0x024
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#define RING_NUM_REQ_TRANS_LS 0x028
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#define RING_NUM_REQ_TRANS_MS 0x02c
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#define RING_NUM_REQ_OUTSTAND 0x030
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#define RING_CONTROL 0x034
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#define RING_FLUSH_DONE 0x038
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#define RING_MSI_ADDR_LS 0x03c
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#define RING_MSI_ADDR_MS 0x040
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#define RING_CMPL_WR_PTR_DDR_CONTROL 0x048
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#define RING_BD_READ_PTR_DDR_CONTROL 0x04c
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#define RING_WRITE_SEQ_NUM 0x050
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#define RING_READ_SEQ_NUM 0x054
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#define RING_BD_MEM_WRITE_ADDRESS 0x058
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#define RING_AXI_BEAT_CNT 0x05c
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#define RING_AXI_BURST_CNT 0x060
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#define RING_MSI_DATA_VALUE 0x064
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#define RING_PACKET_ALIGNMENT_STATUS0 0x068
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#define RING_PACKET_ALIGNMENT_STATUS1 0x06c
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#define RING_PACKET_ALIGNMENT_STATUS2 0x070
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#define RING_DOORBELL_BD_WRITE_COUNT 0x074
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/* RING Manager Common Registers */
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#define RM_COMM_CTRL_REG(_ring) (0x100 * (_ring))
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#define RM_MSI_DEVID_REG(_ring) (0x100 * (_ring) + 0x4)
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#define RM_AE0_AE_CONTROL 0x2000
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#define RM_AE0_NUMBER_OF_PACKETS_RECEIVED_LS_BITS 0x2004
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#define RM_AE0_NUMBER_OF_PACKETS_RECEIVED_MS_BITS 0x2008
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#define RM_AE0_NUMBER_OF_PACKETS_TRANSMITTED_LS_BITS 0x200c
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#define RM_AE0_NUMBER_OF_PACKETS_TRANSMITTED_MS_BITS 0x2010
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#define RM_AE0_OUTSTANDING_PACKET 0x2014
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#define RM_AE0_AE_FLUSH_STATUS 0x2018
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#define RM_AE0_AE_FIFO_WRITE_POINTER 0x201c
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#define RM_AE0_AE_FIFO_READ_POINTER 0x2020
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#define RM_AE1_AE_CONTROL 0x2100
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#define RM_AE1_NUMBER_OF_PACKETS_RECEIVED_LS_BITS 0x2104
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#define RM_AE1_NUMBER_OF_PACKETS_RECEIVED_MS_BITS 0x2108
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#define RM_AE1_NUMBER_OF_PACKETS_TRANSMITTED_LS_BITS 0x210c
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#define RM_AE1_NUMBER_OF_PACKETS_TRANSMITTED_MS_BITS 0x2110
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#define RM_AE1_OUTSTANDING_PACKET 0x2114
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#define RM_AE1_AE_FLUSH_STATUS 0x2118
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#define RM_AE1_AE_FIFO_WRITE_POINTER 0x211c
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#define RM_AE1_AE_FIFO_READ_POINTER 0x2120
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#define RM_COMM_RING_SECURITY_SETTING 0x3000
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#define RM_COMM_CONTROL 0x3008
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#define RM_COMM_TIMER_CONTROL_0 0x300c
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#define RM_COMM_TIMER_CONTROL_1 0x3010
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#define RM_COMM_BD_THRESHOLD 0x3014
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#define RM_COMM_BURST_LENGTH 0x3018
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#define RM_COMM_FIFO_FULL_THRESHOLD 0x301c
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#define RM_COMM_MASK_SEQUENCE_MAX_COUNT 0x3020
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#define RM_COMM_AE_TIMEOUT 0x3024
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#define RM_COMM_RING_OR_AE_STATUS_LOG_ENABLE 0x3028
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#define RM_COMM_RING_FLUSH_TIMEOUT 0x302c
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#define RM_COMM_MEMORY_CONFIGURATION 0x3030
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#define RM_COMM_AXI_CONTROL 0x3034
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#define RM_COMM_GENERAL_MSI_DEVICE_ID 0x3038
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#define RM_COMM_GENERAL_MSI_ADDRESS_LS 0x303c
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#define RM_COMM_GENERAL_MSI_ADDRESS_MS 0x3040
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#define RM_COMM_CONFIG_INTERRUPT_STATUS_MASK 0x3044
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#define RM_COMM_CONFIG_INTERRUPT_STATUS_CLEAR 0x3048
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#define RM_COMM_TOGGLE_INTERRUPT_STATUS_MASK 0x304c
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#define RM_COMM_TOGGLE_INTERRUPT_STATUS_CLEAR 0x3050
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#define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS_MASK 0x3054
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#define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS_CLEAR 0x3058
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#define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS_MASK 0x305c
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#define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS_CLEAR 0x3060
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#define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_MASK 0x3064
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#define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_CLEAR 0x3068
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#define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_MASK 0x306c
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#define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_CLEAR 0x3070
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#define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_MASK 0x3074
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#define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_CLEAR 0x3078
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#define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_MASK 0x307c
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#define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_CLEAR 0x3080
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#define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_MASK 0x3084
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#define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_CLEAR 0x3088
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#define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_MASK 0x308c
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#define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_CLEAR 0x3090
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#define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_MASK 0x3094
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#define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_CLEAR 0x3098
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#define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_MASK 0x309c
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#define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_CLEAR 0x30a0
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#define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS_MASK 0x30a4
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#define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS_CLEAR 0x30a8
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#define RM_COMM_REORDER_INTERRUPT_STATUS_MASK 0x30ac
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#define RM_COMM_REORDER_INTERRUPT_STATUS_CLEAR 0x30b0
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#define RM_COMM_DME_INTERRUPT_STATUS_MASK 0x30b4
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#define RM_COMM_DME_INTERRUPT_STATUS_CLEAR 0x30b8
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#define RM_COMM_REORDER_FIFO_PROG_THRESHOLD 0x30bc
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#define RM_COMM_GROUP_PKT_EXTENSION_SUPPORT 0x30c0
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#define RM_COMM_GENERAL_MSI_DATA_VALUE 0x30c4
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#define RM_COMM_AXI_READ_BURST_THRESHOLD 0x30c8
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#define RM_COMM_GROUP_RING_COUNT 0x30cc
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#define RM_COMM_MSI_DISABLE 0x30d8
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#define RM_COMM_RESERVE 0x30fc
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#define RM_COMM_RING_FLUSH_STATUS 0x3100
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#define RM_COMM_RING_SEQUENCE_NUMBER_OVERFLOW 0x3104
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#define RM_COMM_AE_SEQUENCE_NUMBER_OVERFLOW 0x3108
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#define RM_COMM_MAX_SEQUENCE_NUMBER_FOR_ANY_RING 0x310c
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#define RM_COMM_MAX_SEQUENCE_NUMBER_ON_MONITOR_RING 0x3110
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#define RM_COMM_MAX_SEQUENCE_NUMBER_ON_ANY_AE 0x3114
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#define RM_COMM_MAX_SEQUENCE_NUMBER_ON_MONITOR_AE 0x3118
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#define RM_COMM_MIN_MAX_LATENCY_MONITOR_RING_TOGGLE 0x311c
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#define RM_COMM_MIN_MAX_LATENCY_MONITOR_RING_ADDRESSGEN 0x3120
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#define RM_COMM_RING_ACTIVITY 0x3124
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#define RM_COMM_AE_ACTIVITY 0x3128
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#define RM_COMM_MAIN_HW_INIT_DONE 0x312c
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#define RM_COMM_MEMORY_POWER_STATUS 0x3130
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#define RM_COMM_CONFIG_STATUS_0 0x3134
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#define RM_COMM_CONFIG_STATUS_1 0x3138
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#define RM_COMM_TOGGLE_STATUS_0 0x313c
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#define RM_COMM_TOGGLE_STATUS_1 0x3140
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#define RM_COMM_DDR_ADDR_GEN_STATUS_0 0x3144
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#define RM_COMM_DDR_ADDR_GEN_STATUS_1 0x3148
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_0 0x314c
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_1 0x3150
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_2 0x3154
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_3 0x3158
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#define RM_COMM_AE_INTERFACE_GROUP_0_STATUS_0 0x315c
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#define RM_COMM_AE_INTERFACE_GROUP_0_STATUS_1 0x3160
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#define RM_COMM_AE_INTERFACE_GROUP_1_STATUS_0 0x3164
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#define RM_COMM_AE_INTERFACE_GROUP_1_STATUS_1 0x3168
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#define RM_COMM_AE_INTERFACE_GROUP_2_STATUS_0 0x316c
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#define RM_COMM_AE_INTERFACE_GROUP_2_STATUS_1 0x3170
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#define RM_COMM_AE_INTERFACE_GROUP_3_STATUS_0 0x3174
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#define RM_COMM_AE_INTERFACE_GROUP_3_STATUS_1 0x3178
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#define RM_COMM_AE_INTERFACE_GROUP_4_STATUS_0 0x317c
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#define RM_COMM_AE_INTERFACE_GROUP_4_STATUS_1 0x3180
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#define RM_COMM_AE_INTERFACE_GROUP_5_STATUS_0 0x3184
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#define RM_COMM_AE_INTERFACE_GROUP_5_STATUS_1 0x3188
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#define RM_COMM_AE_INTERFACE_GROUP_6_STATUS_0 0x318c
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#define RM_COMM_AE_INTERFACE_GROUP_6_STATUS_1 0x3190
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#define RM_COMM_AE_INTERFACE_GROUP_7_STATUS_0 0x3194
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#define RM_COMM_AE_INTERFACE_GROUP_7_STATUS_1 0x3198
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#define RM_COMM_AE_INTERFACE_TOP_STATUS_0 0x319c
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#define RM_COMM_AE_INTERFACE_TOP_STATUS_1 0x31a0
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#define RM_COMM_REORDER_STATUS_0 0x31a4
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#define RM_COMM_REORDER_STATUS_1 0x31a8
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#define RM_COMM_REORDER_STATUS_2 0x31ac
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#define RM_COMM_REORDER_STATUS_3 0x31b0
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#define RM_COMM_REORDER_STATUS_4 0x31b4
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#define RM_COMM_REORDER_STATUS_5 0x31b8
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#define RM_COMM_CONFIG_INTERRUPT_STATUS 0x31bc
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#define RM_COMM_TOGGLE_INTERRUPT_STATUS 0x31c0
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#define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS 0x31c4
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#define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS 0x31c8
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#define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_STATUS 0x31cc
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#define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_STATUS 0x31d0
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#define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_STATUS 0x31d4
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#define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_STATUS 0x31d8
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#define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_STATUS 0x31dc
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#define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_STATUS 0x31e0
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#define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_STATUS 0x31e4
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#define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_STATUS 0x31e8
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#define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS 0x31ec
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#define RM_COMM_REORDER_INTERRUPT_STATUS 0x31f0
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#define RM_COMM_DME_INTERRUPT_STATUS 0x31f4
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_4 0x31f8
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_5 0x31fc
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#define RM_COMM_PACKET_ALIGNMENT_STATUS_6 0x3200
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#define RM_COMM_MSI_INTR_INTERRUPT_STATUS 0x3204
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#define RM_COMM_BD_FETCH_MODE_CONTROL 0x3360
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#define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT 16
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#define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT_VAL 32
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#define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_MASK 0x1FF
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#define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_SHIFT 25
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#define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_VAL 40
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#define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_MASK 0x7F
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#define RM_COMM_BD_FIFO_FULL_THRESHOLD_VAL 224
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#define RM_COMM_BD_FIFO_FULL_THRESHOLD_SHIFT 16
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#define RM_COMM_BD_FIFO_FULL_THRESHOLD_MASK 0x1FF
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/* PAX_DMA_RM_COMM_RM_BURST_LENGTH */
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#define RM_COMM_BD_FETCH_CACHE_ALIGNED_DISABLED BIT(28)
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#define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_SHIFT 16
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#define RM_COMM_VALUE_FOR_TOGGLE_SHIFT 0
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#define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_VAL 32
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#define RM_COMM_VALUE_FOR_TOGGLE_VAL 32
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#define RM_COMM_DISABLE_GRP_BD_FIFO_FLOW_CONTROL_FOR_PKT_ALIGNMENT BIT(1)
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#define RM_COMM_DISABLE_PKT_ALIGNMENT_BD_FIFO_FLOW_CONTROL BIT(0)
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/* RM version */
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#define RING_VER_MAGIC 0x76303031
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/* Register RING_CONTROL fields */
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#define RING_CONTROL_MASK_DISABLE_CONTROL 6
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#define RING_CONTROL_FLUSH BIT(5)
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#define RING_CONTROL_ACTIVE BIT(4)
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/* Register RING_FLUSH_DONE fields */
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#define RING_FLUSH_DONE_MASK 0x1
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#define RING_MASK_SEQ_MAX_COUNT_MASK 0x3ff
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/* RM_COMM_MAIN_HW_INIT_DONE DONE fields */
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#define RM_COMM_MAIN_HW_INIT_DONE_MASK 0x1
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/* Register RING_CMPL_WR_PTR_DDR_CONTROL fields */
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#define RING_BD_READ_PTR_DDR_TIMER_VAL_SHIFT 16
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#define RING_BD_READ_PTR_DDR_TIMER_VAL_MASK 0xffff
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#define RING_BD_READ_PTR_DDR_ENABLE_SHIFT 15
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#define RING_BD_READ_PTR_DDR_ENABLE_MASK 0x1
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/* Register RING_BD_READ_PTR_DDR_CONTROL fields */
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#define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_SHIFT 16
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#define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_MASK 0xffff
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#define RING_BD_CMPL_WR_PTR_DDR_ENABLE_SHIFT 15
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#define RING_BD_CMPL_WR_PTR_DDR_ENABLE_MASK 0x1
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/*
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* AE_TIMEOUT is (2^AE_TIMEOUT_BITS) - (2 * NumOfAEs * 2^FIFO_DEPTH_BITS)
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* AE_TIMEOUT_BITS=32, NumOfAEs=2, FIFO_DEPTH_BITS=5
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* timeout val = 2^32 - 2*2*2^5
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*/
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#define RM_COMM_AE_TIMEOUT_VAL 0xffffff80
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/* RM timer control fields for 4 rings */
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#define RM_COMM_TIMER_CONTROL_FAST 0xaf
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#define RM_COMM_TIMER_CONTROL_FAST_SHIFT 16
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#define RM_COMM_TIMER_CONTROL_MEDIUM 0x15e
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#define RM_COMM_TIMER_CONTROL0_VAL \
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((RM_COMM_TIMER_CONTROL_FAST << RM_COMM_TIMER_CONTROL_FAST_SHIFT) | \
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(RM_COMM_TIMER_CONTROL_MEDIUM))
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#define RM_COMM_TIMER_CONTROL_SLOW 0x2bc
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#define RM_COMM_TIMER_CONTROL_SLOW_SHIFT 16
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#define RM_COMM_TIMER_CONTROL_IDLE 0x578
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#define RM_COMM_TIMER_CONTROL1_VAL \
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((RM_COMM_TIMER_CONTROL_SLOW << RM_COMM_TIMER_CONTROL_SLOW_SHIFT) | \
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(RM_COMM_TIMER_CONTROL_IDLE))
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#define RM_COMM_RM_BURST_LENGTH 0x80008
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/* Register RM_COMM_AXI_CONTROL fields */
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#define RM_COMM_AXI_CONTROL_RD_CH_EN_SHIFT 24
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#define RM_COMM_AXI_CONTROL_RD_CH_EN \
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BIT(RM_COMM_AXI_CONTROL_RD_CH_EN_SHIFT)
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#define RM_COMM_AXI_CONTROL_WR_CH_EN_SHIFT 28
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#define RM_COMM_AXI_CONTROL_WR_CH_EN \
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BIT(RM_COMM_AXI_CONTROL_WR_CH_EN_SHIFT)
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/* Register Per-ring RING_COMMON_CONTROL fields */
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#define RING_COMM_CTRL_AE_GROUP_SHIFT 0
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#define RING_COMM_CTRL_AE_GROUP_MASK (0x7 << RING_COMM_CTRL_AE_GROUP_SHIFT)
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/* Register AE0_AE_CONTROL/AE1_AE_CONTROL fields */
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#define RM_AE_CONTROL_ACTIVE BIT(4)
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#define RM_AE_CTRL_AE_GROUP_SHIFT 0
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#define RM_AE_CTRL_AE_GROUP_MASK (0x7 << RM_AE_CTRL_AE_GROUP_SHIFT)
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/* Register RING_CMPL_WR_PTR_DDR_CONTROL fields */
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#define RING_DDR_CONTROL_COUNT_SHIFT 0
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#define RING_DDR_CONTROL_COUNT_MASK 0x3ff
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#define RING_DDR_CONTROL_COUNT(x) (((x) & RING_DDR_CONTROL_COUNT_MASK) \
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<< RING_DDR_CONTROL_COUNT_SHIFT)
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#define RING_DDR_CONTROL_COUNT_VAL 0x1U
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#define RING_DDR_CONTROL_ENABLE_SHIFT 15
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#define RING_DDR_CONTROL_ENABLE BIT(RING_DDR_CONTROL_ENABLE_SHIFT)
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#define RING_DDR_CONTROL_TIMER_SHIFT 16
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#define RING_DDR_CONTROL_TIMER_MASK 0xffff
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#define RING_DDR_CONTROL_TIMER(x) (((x) & RING_DDR_CONTROL_TIMER_MASK) \
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<< RING_DDR_CONTROL_TIMER_SHIFT)
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/*
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* Set no timeout value for completion write path as it would generate
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* multiple interrupts during large transfers. And if timeout value is
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* set, completion write pointers has to be checked on each interrupt
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* to ensure that transfer is actually done.
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*/
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#define RING_DDR_CONTROL_TIMER_VAL (0xFFFF)
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/* completion DME status code */
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#define PAX_DMA_STATUS_AXI_RRESP_ERR BIT(0)
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#define PAX_DMA_STATUS_AXI_BRESP_ERR BIT(1)
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#define PAX_DMA_STATUS_PCIE_CA_ERR BIT(2)
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#define PAX_DMA_STATUS_PCIE_UR_ERR BIT(3)
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#define PAX_DMA_STATUS_PCIE_CMPL_TOUT_ERR BIT(4)
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#define PAX_DMA_STATUS_PCIE_RX_POISON BIT(5)
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#define PAX_DMA_STATUS_ERROR_MASK ( \
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PAX_DMA_STATUS_AXI_RRESP_ERR | \
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PAX_DMA_STATUS_AXI_BRESP_ERR | \
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PAX_DMA_STATUS_PCIE_CA_ERR | \
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PAX_DMA_STATUS_PCIE_UR_ERR | \
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PAX_DMA_STATUS_PCIE_CMPL_TOUT_ERR | \
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PAX_DMA_STATUS_PCIE_RX_POISON \
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)
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/* completion RM status code */
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#define RM_COMPLETION_SUCCESS 0x0
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#define RM_COMPLETION_AE_TIMEOUT 0x3FF
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#define RM_COMM_MSI_CONFIG_INTERRUPT_ACCESS_ERR_MASK BIT(9)
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#define RM_COMM_MSI_CONFIG_INTERRUPT_BRESP_ERR_MASK BIT(8)
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#define RM_COMM_MSI_DISABLE_MASK BIT(0)
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/* Buffer Descriptor definitions */
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#define PAX_DMA_TYPE_RM_HEADER 0x1
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#define PAX_DMA_TYPE_NEXT_PTR 0x5
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/* one desc ring size( is 4K, 4K aligned */
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#define PAX_DMA_RM_DESC_RING_SIZE 4096
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#define PAX_DMA_RING_BD_ALIGN_ORDER 12
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/* completion ring size(bytes) is 8K, 8K aligned */
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#define PAX_DMA_RM_CMPL_RING_SIZE 8192
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#define PAX_DMA_RING_CMPL_ALIGN_ORDER 13
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#define PAX_DMA_RING_BD_ALIGN_CHECK(addr) \
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(!((addr) & ((0x1 << RING_BD_ALIGN_ORDER) - 1)))
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#define RING_CMPL_ALIGN_CHECK(addr) \
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(!((addr) & ((0x1 << RING_CMPL_ALIGN_ORDER) - 1)))
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/* RM descriptor width: 8 bytes */
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#define PAX_DMA_RM_DESC_BDWIDTH 8
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/* completion msg desc takes 1 BD */
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#define PAX_DMA_CMPL_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH
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/* Next table desc takes 1 BD */
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#define PAX_DMA_NEXT_TBL_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH
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/* Header desc takes 1 BD */
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#define PAX_DMA_HEADER_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH
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/* Total BDs in ring: 4K/8bytes = 512 BDs */
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#define PAX_DMA_RM_RING_BD_COUNT (PAX_DMA_RM_DESC_RING_SIZE / \
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PAX_DMA_RM_DESC_BDWIDTH)
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/* Initial RM header is first BD in ring */
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#define PAX_DMA_HEADER_INDEX 0
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#define PAX_DMA_HEADER_ADDR(_ring) (void *)((uintptr_t)(_ring) + \
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PAX_DMA_HEADER_INDEX * PAX_DMA_RM_DESC_BDWIDTH)
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/* NEXT TABLE desc offset is last BD in ring */
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#define PAX_DMA_NEXT_TBL_INDEX (PAX_DMA_RM_RING_BD_COUNT - 1)
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#define PAX_DMA_NEXT_TBL_ADDR(_ring) (void *)((uintptr_t)(_ring) + \
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PAX_DMA_NEXT_TBL_INDEX * PAX_DMA_RM_DESC_BDWIDTH)
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/* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */
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#define PAX_DMA_MIN_SIZE 4
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#define PAX_DMA_MAX_SIZE (16 * 1024 * 1024)
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/* Host and Card address need 4-byte alignment */
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#define PAX_DMA_ADDR_ALIGN 4
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#define RM_RING_REG(_pd, _r, _write_ptr) \
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((_pd)->ring[_r].ring_base + (_write_ptr))
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#define RM_COMM_REG(_pd, _write_ptr) ((_pd)->rm_comm_base + (_write_ptr))
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#define PAX_DMA_REG(_pd, _write_ptr) ((_pd)->dma_base + (_write_ptr))
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#define PAX_DMA_MAX_CMPL_COUNT 1024
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#define PAX_DMA_LAST_CMPL_IDX (PAX_DMA_MAX_CMPL_COUNT - 1)
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#define PAX_DMA_RING_ALIGN BIT(PAX_DMA_RING_CMPL_ALIGN_ORDER)
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/* num of completions received, circular buffer */
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#define PAX_DMA_GET_CMPL_COUNT(wptr, rptr) (((wptr) >= (rptr)) ? \
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((wptr) - (rptr)) : (PAX_DMA_MAX_CMPL_COUNT - (rptr) + (wptr)))
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/* location of current cmpl pkt, take care of pointer wrap-around */
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#define PAX_DMA_CURR_CMPL_IDX(wptr) \
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(((wptr) == 0) ? PAX_DMA_LAST_CMPL_IDX : (wptr) - 1)
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/* Timeout (milliseconds) for completion alert in interrupt mode */
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#define PAX_DMA_TIMEOUT 10000
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|
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/* TODO: add macro to enable data memory barrier, to ensure writes to memory */
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#define dma_mb()
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|
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/* Max polling cycles for completion wait, >= 1 second */
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#define PAX_DMA_MAX_POLL_WAIT 1000000
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/* Max polling cycles for posted write sync >= 1 second */
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#define PAX_DMA_MAX_SYNC_WAIT 1000000
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|
|
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enum ring_idx {
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PAX_DMA_RING0 = 0,
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PAX_DMA_RING1,
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PAX_DMA_RING2,
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PAX_DMA_RING3,
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PAX_DMA_RINGS_MAX
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};
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|
|
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/*
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* DMA direction
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*/
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enum pax_dma_dir {
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CARD_TO_HOST = 0x1,
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HOST_TO_CARD = 0x2
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};
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|
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/* Completion packet */
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struct cmpl_pkt {
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uint64_t opq : 16; /*pkt_id 15:0*/
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uint64_t res : 16; /*reserved 16:31*/
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uint64_t dma_status : 16; /*PAX DMA status 32:47*/
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|
uint64_t ae_num : 6; /*RM status[47:53] processing AE number */
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|
uint64_t rm_status : 10; /*RM status[54:63] completion/timeout status*/
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|
} __attribute__ ((__packed__));
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|
|
|
/* Driver internal structures */
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|
|
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struct dma_iproc_pax_addr64 {
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|
uint32_t addr_lo;
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|
uint32_t addr_hi;
|
|
} __attribute__((__packed__));
|
|
|
|
/* DMA payload for RM internal API */
|
|
struct dma_iproc_pax_payload {
|
|
uint64_t pci_addr;
|
|
uint64_t axi_addr;
|
|
uint32_t xfer_sz;
|
|
enum pax_dma_dir direction;
|
|
};
|
|
|
|
/* magic to sync completion of posted writes to host */
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|
struct dma_iproc_pax_write_sync_data {
|
|
/* sglist count, max 254 */
|
|
uint32_t total_pkts:9;
|
|
/* ring-id 0-3 */
|
|
uint32_t ring:2;
|
|
/* opaque-id 0-31 */
|
|
uint32_t opaque:5;
|
|
/* magic pattern */
|
|
uint32_t signature:16;
|
|
};
|
|
|
|
/* BD ring status */
|
|
struct dma_iproc_pax_ring_status {
|
|
/* current desc write_ptret, write pointer */
|
|
void *write_ptr;
|
|
/* current valid toggle */
|
|
uint32_t toggle;
|
|
/* completion queue read offset */
|
|
uint32_t cmpl_rd_offs;
|
|
/* opaque value for current payload */
|
|
uint32_t opq;
|
|
/* posted write sync data */
|
|
struct dma_iproc_pax_write_sync_data sync_data;
|
|
};
|
|
|
|
struct dma_iproc_pax_ring_data {
|
|
/* ring index */
|
|
uint32_t idx;
|
|
/* Per-Ring register base */
|
|
uint32_t ring_base;
|
|
/* Allocated mem for BD and CMPL */
|
|
void *ring_mem;
|
|
/* Buffer descriptors, 4K aligned */
|
|
void *bd;
|
|
/* Completion descriptors, 8K aligned */
|
|
void *cmpl;
|
|
/* payload struct for internal API */
|
|
struct dma_iproc_pax_payload *payload;
|
|
/* ring current status */
|
|
struct dma_iproc_pax_ring_status curr;
|
|
/* assigned packet id upto 32 values */
|
|
uint32_t pkt_id;
|
|
/* per-ring lock */
|
|
struct k_mutex lock;
|
|
/* alert for the ring */
|
|
struct k_sem alert;
|
|
/* posted write sync src location */
|
|
struct dma_iproc_pax_write_sync_data *sync_loc;
|
|
/* posted write sync pci dst address */
|
|
struct dma_iproc_pax_addr64 sync_pci;
|
|
/* ring status */
|
|
int ring_active;
|
|
/* dma callback and argument */
|
|
dma_callback_t dma_callback;
|
|
void *callback_arg;
|
|
uint32_t descs_inflight;
|
|
uint32_t non_hdr_bd_count;
|
|
uint32_t total_pkt_count;
|
|
uintptr_t current_hdr;
|
|
};
|
|
|
|
struct dma_iproc_pax_data {
|
|
/* PAXB0 PAX DMA registers */
|
|
uint32_t dma_base;
|
|
/* Ring manager common registers */
|
|
uint32_t rm_comm_base;
|
|
/* Num of rings to use in s/w */
|
|
int used_rings;
|
|
/* DMA lock */
|
|
struct k_mutex dma_lock;
|
|
/* Per-Ring data */
|
|
struct dma_iproc_pax_ring_data ring[PAX_DMA_RINGS_MAX];
|
|
};
|
|
|
|
/* PAX DMA config */
|
|
struct dma_iproc_pax_cfg {
|
|
/* PAXB0 PAX DMA registers */
|
|
uint32_t dma_base;
|
|
/* Per-Ring register base addr */
|
|
uint32_t rm_base;
|
|
/* Ring manager common registers */
|
|
uint32_t rm_comm_base;
|
|
/* Num of rings to be used */
|
|
int use_rings;
|
|
void *bd_memory_base;
|
|
uint32_t scr_addr_loc;
|
|
const struct device *pcie_dev;
|
|
};
|
|
|
|
#endif
|