55 lines
1.1 KiB
Plaintext
55 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2023 Evan Perry Grove
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f7/stm32f7.dtsi>
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/ {
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/* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
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* 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
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*/
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sram0: memory@20010000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(192)>;
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zephyr,memory-region = "SRAM0";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "DTCM";
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};
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itcm: memory@0 {
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compatible = "zephyr,memory-region", "arm,itcm";
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reg = <0x00000000 DT_SIZE_K(16)>;
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zephyr,memory-region = "ITCM";
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};
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soc {
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compatible = "st,stm32f722", "st,stm32f7", "simple-bus";
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sdmmc2: sdmmc@40011c00 {
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compatible = "st,stm32-sdmmc";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
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<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
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resets = <&rctl STM32_RESET(APB2, 7U)>;
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interrupts = <103 0>;
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status = "disabled";
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};
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};
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die_temp: dietemp {
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ts-cal1-addr = <0x1FF07A2C>;
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ts-cal2-addr = <0x1FF07A2E>;
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};
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vref: vref {
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vrefint-cal-addr = <0x1FF07A2A>;
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};
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};
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