290 lines
7.0 KiB
Plaintext
290 lines
7.0 KiB
Plaintext
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2021 Marius Scholtz, RIC Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f401.dtsi>
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/ {
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chosen {
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zephyr,entropy = &rng;
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};
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soc {
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compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
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pinctrl: pin-controller@40020000 {
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reg = <0x40020000 0x2400>;
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gpiof: gpio@40021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
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};
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gpiog: gpio@40021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
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};
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gpioi: gpio@40022000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
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};
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1, 18U)>;
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interrupts = <39 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible ="st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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resets = <&rctl STM32_RESET(APB1, 4U)>;
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interrupts = <54 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1, 5U)>;
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interrupts = <55 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers8: timers@40010400 {
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compatible = "st,stm32-timers";
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reg = <0x40010400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
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resets = <&rctl STM32_RESET(APB2, 1U)>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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qdec {
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compatible = "st,stm32-qdec";
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status = "disabled";
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st,input-filter-level = <NO_FILTER>;
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};
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};
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timers12: timers@40001800 {
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
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resets = <&rctl STM32_RESET(APB1, 6U)>;
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interrupts = <43 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers13: timers@40001c00 {
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compatible = "st,stm32-timers";
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reg = <0x40001c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
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resets = <&rctl STM32_RESET(APB1, 7U)>;
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interrupts = <44 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
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resets = <&rctl STM32_RESET(APB1, 8U)>;
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interrupts = <45 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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usbotg_hs: usb@40040000 {
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compatible = "st,stm32-otghs";
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reg = <0x40040000 0x40000>;
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interrupts = <77 0>, <74 0>, <75 0>;
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interrupt-names = "otghs", "ep1_out", "ep1_in";
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num-bidir-endpoints = <6>;
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ram-size = <4096>;
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maximum-speed = "full-speed";
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phys = <&otghs_fs_phy>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
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<&rcc STM32_SRC_PLL_Q NO_SEL>;
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status = "disabled";
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};
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can1: can@40006400 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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};
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can2: can@40006800 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006800 0x400>;
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interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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/* also enabling clock for can1 (master instance) */
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
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master-can-reg = <0x40006400>;
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status = "disabled";
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};
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rng: rng@50060800 {
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compatible = "st,stm32-rng";
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reg = <0x50060800 0x400>;
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interrupts = <80 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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status = "disabled";
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};
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backup_sram: memory@40024000 {
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compatible = "zephyr,memory-region", "st,stm32-backup-sram";
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reg = <0x40024000 DT_SIZE_K(4)>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
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zephyr,memory-region = "BACKUP_SRAM";
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status = "disabled";
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};
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adc2: adc@40012100 {
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compatible = "st,stm32-adc";
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reg = <0x40012100 0x050>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 15 28 56 84 112 144 480>;
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st,adc-clock-source = <SYNC>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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adc3: adc@40012200 {
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compatible = "st,stm32-adc";
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reg = <0x40012200 0x050>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 15 28 56 84 112 144 480>;
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st,adc-clock-source = <SYNC>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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otghs_fs_phy: otghs_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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