80 lines
2.2 KiB
Plaintext
80 lines
2.2 KiB
Plaintext
# SOF DMIC configuration options
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config DAI_INTEL_DMIC
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bool "Intel digital PDM microphone driver support for DAI interface"
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default y
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depends on DT_HAS_INTEL_DAI_DMIC_ENABLED
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depends on PM_DEVICE_RUNTIME
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help
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Enable Intel digital PDM microphone driver for DAI interface
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if DAI_INTEL_DMIC
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choice
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prompt "Driver operation mode"
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default DAI_INTEL_DMIC_NHLT
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help
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The driver can support two operation modes.
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1. A HW registers dump blob that is passed via IPC
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2. DAI tokens those describe the use case PCM format
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and PDM bus and microphone parameters
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config DAI_INTEL_DMIC_NHLT
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bool "Use NHLT DMIC blob"
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help
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All registers configuration is retrieved from blob. The
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number of channels, sample rate, and PCM format are
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defined in the blob and there are no runtime made
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configuration choices.
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config DAI_INTEL_DMIC_TPLG_PARAMS
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bool "Use parameters from topology - WIP"
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help
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All registers configuration is computed on the fly
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based on use case and microphone datasheet parameters
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and topology defined PCM format. The parameters are
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easy to to customize in the topology.
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WORK IN PROGRESS, not enabled in the driver yet
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endchoice
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config DAI_DMIC_HAS_OWNERSHIP
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bool "Use DMIC ownership claim/release"
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default n
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help
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a feature introduced in ACE1.5 hardware
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dmic ownership must be claimed before use of dmic
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config DAI_DMIC_HAS_MULTIPLE_LINE_SYNC
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bool "Use DMIC sync for multiple lines"
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default n
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help
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a feature introduced in ACE1.5 hardware
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dmic sync registers must be set before use of dmic
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config DAI_DMIC_HW_CONTROLLERS
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int "Number of hardware controllers in the system"
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default 2
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config DAI_DMIC_HW_FIFOS
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int "Number of stream FIFOs in DMIC controller"
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default 2
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config DAI_DMIC_HW_IOCLK
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int "IO Clock value for DMIC"
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default 19200000
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config DAI_DMIC_PLATFORM_SYNC_PERIOD
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int "Sync period per platform"
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default 4000
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help
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DMIC sync period used for:
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CONFIG_DAI_DMIC_HW_IOCLK / CONFIG_DAI_DMIC_PLATFORM_SYNC_PERIOD
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From spec: E.g. for 19.2 MHz XTAL oscillator clock, 4 KHz sync period,
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the value to be programmed is 4799 (12BFh)
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endif
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