zephyr/arch/xtensa/core
Flavio Ceolin f74a84b251 xtensa: mmu: MMU re-initialization API
With power managment is enabled, depending on the SoC power state
used when idle, the MMU may lose context and may need to be re-initialized.
When re-initializing the MMU, we must not re-create the page table
because it may overwrite changes done during the execution, but we still
need to set the asid and page table for the current context.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 16:27:55 -05:00
..
offsets
startup
CMakeLists.txt build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
README_MMU.txt
README_WINDOWS.rst
coredump.c arch: define `struct arch_esf` and deprecate `z_arch_esf_t` 2024-06-04 14:02:51 -05:00
cpu_idle.c
crt1.S
debug_helpers_asm.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
elf.c
fatal.c arch: define `struct arch_esf` and deprecate `z_arch_esf_t` 2024-06-04 14:02:51 -05:00
gdbstub.c arch: define `struct arch_esf` and deprecate `z_arch_esf_t` 2024-06-04 14:02:51 -05:00
gen_vectors.py arch/xtensa: Add automatic vector linkage generation 2024-05-22 13:39:47 -05:00
gen_zsr.py
irq_manage.c
irq_offload.c build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
mem_manage.c
mmu.c
mpu.c
ptables.c xtensa: mmu: MMU re-initialization API 2024-06-04 16:27:55 -05:00
smp.c
syscall_helper.c
thread.c
timing.c
tls.c
userspace.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
vector_handlers.c arch: define `struct arch_esf` and deprecate `z_arch_esf_t` 2024-06-04 14:02:51 -05:00
window_vectors.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
xcc_stubs.c
xtensa_asm2_util.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
xtensa_backtrace.c
xtensa_hifi.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
xtensa_intgen.py arch/xtensa: xtensa_intgen.py: Emit handlers for all levels 2024-05-20 20:50:55 -04:00
xtensa_intgen.tmpl