504 lines
14 KiB
C
504 lines
14 KiB
C
/*
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* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT xlnx_xps_spi_2_00_a
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#include <zephyr/device.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(xlnx_quadspi, CONFIG_SPI_LOG_LEVEL);
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#include "spi_context.h"
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/* AXI Quad SPI v3.2 register offsets (See Xilinx PG153 for details) */
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#define SRR_OFFSET 0x40
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#define SPICR_OFFSET 0x60
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#define SPISR_OFFSET 0x64
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#define SPI_DTR_OFFSET 0x68
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#define SPI_DRR_OFFSET 0x6c
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#define SPISSR_OFFSET 0x70
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#define SPI_TX_FIFO_OCR_OFFSET 0x74
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#define SPI_RX_FIFO_OCR_OFFSET 0x78
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#define DGIER_OFFSET 0x1c
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#define IPISR_OFFSET 0x20
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#define IPIER_OFFSET 0x28
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/* SRR bit definitions */
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#define SRR_SOFTRESET_MAGIC 0xa
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/* SPICR bit definitions */
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#define SPICR_LOOP BIT(0)
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#define SPICR_SPE BIT(1)
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#define SPICR_MASTER BIT(2)
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#define SPICR_CPOL BIT(3)
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#define SPICR_CPHA BIT(4)
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#define SPICR_TX_FIFO_RESET BIT(5)
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#define SPICR_RX_FIFO_RESET BIT(6)
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#define SPICR_MANUAL_SS BIT(7)
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#define SPICR_MASTER_XFER_INH BIT(8)
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#define SPICR_LSB_FIRST BIT(9)
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/* SPISR bit definitions */
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#define SPISR_RX_EMPTY BIT(0)
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#define SPISR_RX_FULL BIT(1)
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#define SPISR_TX_EMPTY BIT(2)
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#define SPISR_TX_FULL BIT(3)
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#define SPISR_MODF BIT(4)
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#define SPISR_SLAVE_MODE_SELECT BIT(5)
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#define SPISR_CPOL_CPHA_ERROR BIT(6)
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#define SPISR_SLAVE_MODE_ERROR BIT(7)
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#define SPISR_MSB_ERROR BIT(8)
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#define SPISR_LOOPBACK_ERROR BIT(9)
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#define SPISR_COMMAND_ERROR BIT(10)
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#define SPISR_ERROR_MASK (SPISR_COMMAND_ERROR | \
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SPISR_LOOPBACK_ERROR | \
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SPISR_MSB_ERROR | \
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SPISR_SLAVE_MODE_ERROR | \
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SPISR_CPOL_CPHA_ERROR)
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/* DGIER bit definitions */
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#define DGIER_GIE BIT(31)
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/* IPISR and IPIER bit definitions */
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#define IPIXR_MODF BIT(0)
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#define IPIXR_SLAVE_MODF BIT(1)
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#define IPIXR_DTR_EMPTY BIT(2)
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#define IPIXR_DTR_UNDERRUN BIT(3)
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#define IPIXR_DRR_FULL BIT(4)
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#define IPIXR_DRR_OVERRUN BIT(5)
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#define IPIXR_TX_FIFO_HALF_EMPTY BIT(6)
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#define IPIXR_SLAVE_MODE_SELECT BIT(7)
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#define IPIXR_DDR_NOT_EMPTY BIT(8)
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#define IPIXR_CPOL_CPHA_ERROR BIT(9)
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#define IPIXR_SLAVE_MODE_ERROR BIT(10)
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#define IPIXR_MSB_ERROR BIT(11)
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#define IPIXR_LOOPBACK_ERROR BIT(12)
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#define IPIXR_COMMAND_ERROR BIT(13)
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struct xlnx_quadspi_config {
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mm_reg_t base;
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void (*irq_config_func)(const struct device *dev);
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uint8_t num_ss_bits;
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uint8_t num_xfer_bytes;
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};
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struct xlnx_quadspi_data {
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struct spi_context ctx;
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};
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static inline uint32_t xlnx_quadspi_read32(const struct device *dev,
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mm_reg_t offset)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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return sys_read32(config->base + offset);
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}
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static inline void xlnx_quadspi_write32(const struct device *dev,
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uint32_t value,
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mm_reg_t offset)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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sys_write32(value, config->base + offset);
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}
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static void xlnx_quadspi_cs_control(const struct device *dev, bool on)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t spissr = BIT_MASK(config->num_ss_bits);
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if (IS_ENABLED(CONFIG_SPI_SLAVE) && spi_context_is_slave(ctx)) {
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/* Skip slave select assert/de-assert in slave mode */
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return;
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}
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if (on) {
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/* SPISSR is one-hot, active-low */
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spissr &= ~BIT(ctx->config->slave);
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} else if (ctx->config->operation & SPI_HOLD_ON_CS) {
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/* Skip slave select de-assert */
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return;
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}
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xlnx_quadspi_write32(dev, spissr, SPISSR_OFFSET);
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spi_context_cs_control(ctx, on);
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}
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static int xlnx_quadspi_configure(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t word_size;
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uint32_t spicr;
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uint32_t spisr;
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if (spi_context_configured(ctx, spi_cfg)) {
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/* Configuration already active, just enable SPI IOs */
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spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);
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spicr |= SPICR_SPE;
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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return 0;
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}
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if (spi_cfg->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (spi_cfg->slave >= config->num_ss_bits) {
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LOG_ERR("unsupported slave %d, num_ss_bits %d",
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spi_cfg->slave, config->num_ss_bits);
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return -ENOTSUP;
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}
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if (spi_cfg->operation & SPI_CS_ACTIVE_HIGH) {
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LOG_ERR("unsupported CS polarity active high");
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return -ENOTSUP;
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}
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if (!IS_ENABLED(CONFIG_SPI_SLAVE) && \
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(spi_cfg->operation & SPI_OP_MODE_SLAVE)) {
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LOG_ERR("slave mode support not enabled");
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return -ENOTSUP;
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}
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (word_size != (config->num_xfer_bytes * 8)) {
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LOG_ERR("unsupported word size %d bits, num_xfer_bytes %d",
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word_size, config->num_xfer_bytes);
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return -ENOTSUP;
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}
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/* Reset FIFOs, SPI IOs enabled */
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spicr = SPICR_TX_FIFO_RESET | SPICR_RX_FIFO_RESET | SPICR_SPE;
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/* Master mode, inhibit master transmit, manual slave select */
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if (!IS_ENABLED(CONFIG_SPI_SLAVE) ||
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(spi_cfg->operation & SPI_OP_MODE_SLAVE) == 0U) {
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spicr |= SPICR_MASTER | SPICR_MASTER_XFER_INH | SPICR_MANUAL_SS;
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}
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if (spi_cfg->operation & SPI_MODE_CPOL) {
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spicr |= SPICR_CPOL;
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}
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if (spi_cfg->operation & SPI_MODE_CPHA) {
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spicr |= SPICR_CPHA;
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}
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if (spi_cfg->operation & SPI_MODE_LOOP) {
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spicr |= SPICR_LOOP;
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}
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if (spi_cfg->operation & SPI_TRANSFER_LSB) {
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spicr |= SPICR_LSB_FIRST;
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}
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/*
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* Write configuration and verify it is compliant with the IP core
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* configuration. Tri-state SPI IOs on error.
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*/
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);
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if (spisr & SPISR_ERROR_MASK) {
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LOG_ERR("unsupported configuration, spisr = 0x%08x", spisr);
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xlnx_quadspi_write32(dev, SPICR_MASTER_XFER_INH, SPICR_OFFSET);
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ctx->config = NULL;
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return -ENOTSUP;
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}
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ctx->config = spi_cfg;
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return 0;
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}
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static void xlnx_quadspi_start_tx(const struct device *dev)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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size_t xfer_len;
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uint32_t spicr = 0U;
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uint32_t spisr;
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uint32_t dtr = 0U;
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if (!spi_context_tx_on(ctx) && !spi_context_rx_on(ctx)) {
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/* All done, de-assert slave select */
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xlnx_quadspi_cs_control(dev, false);
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if ((ctx->config->operation & SPI_HOLD_ON_CS) == 0U) {
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/* Tri-state SPI IOs */
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spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);
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spicr &= ~(SPICR_SPE);
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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}
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spi_context_complete(ctx, 0);
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return;
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}
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if (!IS_ENABLED(CONFIG_SPI_SLAVE) || !spi_context_is_slave(ctx)) {
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/* Inhibit master transaction while writing TX data */
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spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);
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spicr |= SPICR_MASTER_XFER_INH;
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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}
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/* We can only see as far as the current rx buffer */
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xfer_len = spi_context_longest_current_buf(ctx);
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/* Write TX data */
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while (xfer_len--) {
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if (spi_context_tx_buf_on(ctx)) {
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switch (config->num_xfer_bytes) {
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case 1:
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dtr = UNALIGNED_GET((uint8_t *)(ctx->tx_buf));
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break;
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case 2:
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dtr = UNALIGNED_GET((uint16_t *)(ctx->tx_buf));
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break;
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case 4:
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dtr = UNALIGNED_GET((uint32_t *)(ctx->tx_buf));
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break;
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default:
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__ASSERT(0, "unsupported num_xfer_bytes");
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}
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} else {
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/* No TX buffer. Use dummy TX data */
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dtr = 0U;
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}
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xlnx_quadspi_write32(dev, dtr, SPI_DTR_OFFSET);
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spi_context_update_tx(ctx, config->num_xfer_bytes, 1);
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spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);
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if (spisr & SPISR_TX_FULL) {
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break;
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}
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}
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spisr = xlnx_quadspi_read32(dev, SPISR_OFFSET);
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if (spisr & SPISR_COMMAND_ERROR) {
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/* Command not supported by memory type configured in IP core */
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LOG_ERR("unsupported command");
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xlnx_quadspi_cs_control(dev, false);
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spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);
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if ((ctx->config->operation & SPI_HOLD_ON_CS) == 0U) {
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/* Tri-state SPI IOs */
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spicr &= ~(SPICR_SPE);
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}
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xlnx_quadspi_write32(dev, spicr | SPICR_TX_FIFO_RESET,
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SPICR_OFFSET);
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spi_context_complete(ctx, -ENOTSUP);
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}
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if (!IS_ENABLED(CONFIG_SPI_SLAVE) || !spi_context_is_slave(ctx)) {
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/* Uninhibit master transaction */
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spicr &= ~(SPICR_MASTER_XFER_INH);
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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}
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}
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static int xlnx_quadspi_transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool async, struct k_poll_signal *signal)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret;
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spi_context_lock(ctx, async, signal, spi_cfg);
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ret = xlnx_quadspi_configure(dev, spi_cfg);
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if (ret) {
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goto out;
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}
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs,
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config->num_xfer_bytes);
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xlnx_quadspi_cs_control(dev, true);
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xlnx_quadspi_start_tx(dev);
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ret = spi_context_wait_for_completion(ctx);
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out:
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spi_context_release(ctx, ret);
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return ret;
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}
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static int xlnx_quadspi_transceive_blocking(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return xlnx_quadspi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, false,
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NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int xlnx_quadspi_transceive_async(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *signal)
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{
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return xlnx_quadspi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, true,
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signal);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int xlnx_quadspi_release(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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uint32_t spicr;
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/* Force slave select de-assert */
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xlnx_quadspi_write32(dev, BIT_MASK(config->num_ss_bits), SPISSR_OFFSET);
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/* Tri-state SPI IOs */
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spicr = xlnx_quadspi_read32(dev, SPICR_OFFSET);
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spicr &= ~(SPICR_SPE);
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xlnx_quadspi_write32(dev, spicr, SPICR_OFFSET);
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static void xlnx_quadspi_isr(const struct device *dev)
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{
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t temp;
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uint32_t drr;
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/* Acknowledge interrupt */
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temp = xlnx_quadspi_read32(dev, IPISR_OFFSET);
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xlnx_quadspi_write32(dev, temp, IPISR_OFFSET);
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if (temp & IPIXR_DTR_EMPTY) {
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temp = xlnx_quadspi_read32(dev, SPISR_OFFSET);
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/* Read RX data */
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while (!(temp & SPISR_RX_EMPTY)) {
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drr = xlnx_quadspi_read32(dev, SPI_DRR_OFFSET);
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if (spi_context_rx_buf_on(ctx)) {
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switch (config->num_xfer_bytes) {
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case 1:
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UNALIGNED_PUT(drr,
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(uint8_t *)ctx->rx_buf);
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break;
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case 2:
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UNALIGNED_PUT(drr,
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(uint16_t *)ctx->rx_buf);
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break;
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case 4:
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UNALIGNED_PUT(drr,
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(uint32_t *)ctx->rx_buf);
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break;
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default:
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__ASSERT(0,
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"unsupported num_xfer_bytes");
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}
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}
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spi_context_update_rx(ctx, config->num_xfer_bytes, 1);
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temp = xlnx_quadspi_read32(dev, SPISR_OFFSET);
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}
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/* Start next TX */
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xlnx_quadspi_start_tx(dev);
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} else {
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LOG_WRN("unhandled interrupt, ipisr = 0x%08x", temp);
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}
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}
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static int xlnx_quadspi_init(const struct device *dev)
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{
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int err;
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const struct xlnx_quadspi_config *config = dev->config;
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struct xlnx_quadspi_data *data = dev->data;
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/* Reset controller */
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xlnx_quadspi_write32(dev, SRR_SOFTRESET_MAGIC, SRR_OFFSET);
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config->irq_config_func(dev);
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/* Enable DTR Empty interrupt */
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xlnx_quadspi_write32(dev, IPIXR_DTR_EMPTY, IPIER_OFFSET);
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xlnx_quadspi_write32(dev, DGIER_GIE, DGIER_OFFSET);
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err = spi_context_cs_configure_all(&data->ctx);
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if (err < 0) {
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return err;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct spi_driver_api xlnx_quadspi_driver_api = {
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.transceive = xlnx_quadspi_transceive_blocking,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = xlnx_quadspi_transceive_async,
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#endif /* CONFIG_SPI_ASYNC */
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.release = xlnx_quadspi_release,
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};
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#define XLNX_QUADSPI_INIT(n) \
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static void xlnx_quadspi_config_func_##n(const struct device *dev); \
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\
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static const struct xlnx_quadspi_config xlnx_quadspi_config_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.irq_config_func = xlnx_quadspi_config_func_##n, \
|
|
.num_ss_bits = DT_INST_PROP(n, xlnx_num_ss_bits), \
|
|
.num_xfer_bytes = \
|
|
DT_INST_PROP(n, xlnx_num_transfer_bits) / 8, \
|
|
}; \
|
|
\
|
|
static struct xlnx_quadspi_data xlnx_quadspi_data_##n = { \
|
|
SPI_CONTEXT_INIT_LOCK(xlnx_quadspi_data_##n, ctx), \
|
|
SPI_CONTEXT_INIT_SYNC(xlnx_quadspi_data_##n, ctx), \
|
|
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
|
|
}; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, &xlnx_quadspi_init, \
|
|
NULL, \
|
|
&xlnx_quadspi_data_##n, \
|
|
&xlnx_quadspi_config_##n, POST_KERNEL, \
|
|
CONFIG_SPI_INIT_PRIORITY, \
|
|
&xlnx_quadspi_driver_api); \
|
|
\
|
|
static void xlnx_quadspi_config_func_##n(const struct device *dev) \
|
|
{ \
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
|
|
xlnx_quadspi_isr, \
|
|
DEVICE_DT_INST_GET(n), 0); \
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
}
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(XLNX_QUADSPI_INIT)
|