567 lines
17 KiB
C
567 lines
17 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_uart
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#include <zephyr/sys/__assert.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/kernel.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <soc.h>
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#include "soc_miwu.h"
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#include "soc_power.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(uart_npcx, CONFIG_UART_LOG_LEVEL);
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/* Driver config */
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struct uart_npcx_config {
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struct uart_reg *inst;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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/* clock configuration */
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struct npcx_clk_cfg clk_cfg;
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/* int-mux configuration */
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const struct npcx_wui uart_rx_wui;
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/* pinmux configuration */
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const struct pinctrl_dev_config *pcfg;
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};
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enum uart_pm_policy_state_flag {
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UART_PM_POLICY_STATE_TX_FLAG,
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UART_PM_POLICY_STATE_RX_FLAG,
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UART_PM_POLICY_STATE_FLAG_COUNT,
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};
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/* Driver data */
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struct uart_npcx_data {
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/* Baud rate */
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uint32_t baud_rate;
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struct miwu_dev_callback uart_rx_cb;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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#endif
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#ifdef CONFIG_PM
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ATOMIC_DEFINE(pm_policy_state_flag, UART_PM_POLICY_STATE_FLAG_COUNT);
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#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
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struct k_work_delayable rx_refresh_timeout_work;
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#endif
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#endif
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};
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#if defined(CONFIG_PM) && defined(CONFIG_UART_INTERRUPT_DRIVEN)
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static void uart_npcx_pm_policy_state_lock_get(struct uart_npcx_data *data,
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enum uart_pm_policy_state_flag flag)
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{
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if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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}
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static void uart_npcx_pm_policy_state_lock_put(struct uart_npcx_data *data,
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enum uart_pm_policy_state_flag flag)
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{
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if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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}
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#endif /* defined(CONFIG_PM) && defined(CONFIG_UART_INTERRUPT_DRIVEN) */
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/* UART local functions */
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static int uart_set_npcx_baud_rate(struct uart_reg *const inst, int baud_rate, int src_clk)
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{
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/* Fix baud rate to 115200 so far */
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if (baud_rate == 115200) {
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if (src_clk == 15000000) {
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inst->UPSR = 0x38;
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inst->UBAUD = 0x01;
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} else if (src_clk == 20000000) {
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inst->UPSR = 0x08;
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inst->UBAUD = 0x0a;
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} else {
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return -EINVAL;
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}
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} else {
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return -EINVAL;
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}
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_npcx_tx_fifo_ready(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* True if the Tx FIFO is not completely full */
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return !(GET_FIELD(inst->UFTSTS, NPCX_UFTSTS_TEMPTY_LVL) == 0);
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}
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static int uart_npcx_rx_fifo_available(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* True if at least one byte is in the Rx FIFO */
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return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);
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}
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static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* Disable all Tx interrupts */
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inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
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BIT(NPCX_UFTCTL_TEMPTY_EN) |
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BIT(NPCX_UFTCTL_NXMIP_EN));
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}
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static void uart_npcx_clear_rx_fifo(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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uint8_t scratch;
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/* Read all dummy bytes out from Rx FIFO */
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while (uart_npcx_rx_fifo_available(dev))
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scratch = inst->URBUF;
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}
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static int uart_npcx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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uint8_t tx_bytes = 0U;
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/* If Tx FIFO is still ready to send */
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while ((size - tx_bytes > 0) && uart_npcx_tx_fifo_ready(dev)) {
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/* Put a character into Tx FIFO */
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#ifdef CONFIG_PM
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struct uart_npcx_data *data = dev->data;
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uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_TX_FLAG);
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inst->UTBUF = tx_data[tx_bytes++];
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inst->UFTCTL |= BIT(NPCX_UFTCTL_NXMIP_EN);
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#else
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inst->UTBUF = tx_data[tx_bytes++];
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#endif /* CONFIG_PM */
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}
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return tx_bytes;
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}
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static int uart_npcx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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unsigned int rx_bytes = 0U;
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/* If least one byte is in the Rx FIFO */
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while ((size - rx_bytes > 0) && uart_npcx_rx_fifo_available(dev)) {
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/* Receive one byte from Rx FIFO */
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rx_data[rx_bytes++] = inst->URBUF;
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}
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return rx_bytes;
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}
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static void uart_npcx_irq_tx_enable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UFTCTL |= BIT(NPCX_UFTCTL_TEMPTY_EN);
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}
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static void uart_npcx_irq_tx_disable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_EN));
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}
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static int uart_npcx_irq_tx_ready(const struct device *dev)
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{
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return uart_npcx_tx_fifo_ready(dev);
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}
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static int uart_npcx_irq_tx_complete(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* Tx FIFO is empty or last byte is sending */
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return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);
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}
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static void uart_npcx_irq_rx_enable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UFRCTL |= BIT(NPCX_UFRCTL_RNEMPTY_EN);
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}
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static void uart_npcx_irq_rx_disable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UFRCTL &= ~(BIT(NPCX_UFRCTL_RNEMPTY_EN));
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}
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static int uart_npcx_irq_rx_ready(const struct device *dev)
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{
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return uart_npcx_rx_fifo_available(dev);
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}
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static void uart_npcx_irq_err_enable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UICTRL |= BIT(NPCX_UICTRL_EEI);
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}
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static void uart_npcx_irq_err_disable(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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inst->UICTRL &= ~(BIT(NPCX_UICTRL_EEI));
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}
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static int uart_npcx_irq_is_pending(const struct device *dev)
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{
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return (uart_npcx_irq_tx_ready(dev) || uart_npcx_irq_rx_ready(dev));
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}
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static int uart_npcx_irq_update(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_npcx_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_npcx_data *data = dev->data;
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data->user_cb = cb;
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data->user_data = cb_data;
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}
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static void uart_npcx_isr(const struct device *dev)
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{
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struct uart_npcx_data *data = dev->data;
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/*
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* Set pm constraint to prevent the system enter suspend state within
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* the CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT period.
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*/
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#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
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if (uart_npcx_irq_rx_ready(dev)) {
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k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
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uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_RX_FLAG);
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k_work_reschedule(&data->rx_refresh_timeout_work, delay);
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}
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#endif
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if (data->user_cb) {
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data->user_cb(dev, data->user_data);
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}
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#ifdef CONFIG_PM
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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if (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_NXMIP_EN) &&
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IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP)) {
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uart_npcx_pm_policy_state_lock_put(data, UART_PM_POLICY_STATE_TX_FLAG);
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inst->UFTCTL &= ~BIT(NPCX_UFTCTL_NXMIP_EN);
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}
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#endif /* CONFIG_PM */
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}
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/*
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* Poll-in implementation for interrupt driven config, forward call to
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* uart_npcx_fifo_read().
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*/
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static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
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{
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return uart_npcx_fifo_read(dev, c, 1) ? 0 : -1;
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}
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/*
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* Poll-out implementation for interrupt driven config, forward call to
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* uart_npcx_fifo_fill().
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*/
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static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
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{
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while (!uart_npcx_fifo_fill(dev, &c, 1))
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continue;
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}
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#else /* !CONFIG_UART_INTERRUPT_DRIVEN */
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/*
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* Poll-in implementation for byte mode config, read byte from URBUF if
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* available.
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*/
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static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* Rx single byte buffer is not full */
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if (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_RBF))
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return -1;
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*c = inst->URBUF;
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return 0;
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}
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/*
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* Poll-out implementation for byte mode config, write byte to UTBUF if empty.
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*/
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static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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/* Wait while Tx single byte buffer is ready to send */
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while (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_TBE))
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continue;
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inst->UTBUF = c;
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}
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#endif /* !CONFIG_UART_INTERRUPT_DRIVEN */
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/* UART api functions */
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static int uart_npcx_err_check(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_reg *const inst = config->inst;
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uint32_t err = 0U;
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uint8_t stat = inst->USTAT;
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if (IS_BIT_SET(stat, NPCX_USTAT_DOE))
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err |= UART_ERROR_OVERRUN;
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if (IS_BIT_SET(stat, NPCX_USTAT_PE))
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err |= UART_ERROR_PARITY;
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if (IS_BIT_SET(stat, NPCX_USTAT_FE))
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err |= UART_ERROR_FRAMING;
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return err;
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}
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static __unused void uart_npcx_rx_wk_isr(const struct device *dev, struct npcx_wui *wui)
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{
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/*
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* Set pm constraint to prevent the system enter suspend state within
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* the CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT period.
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*/
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#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
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struct uart_npcx_data *data = dev->data;
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k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
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uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_RX_FLAG);
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k_work_reschedule(&data->rx_refresh_timeout_work, delay);
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#endif
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/*
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* Disable MIWU CR_SIN interrupt to avoid the other redundant interrupts
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* after ec wakes up.
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*/
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npcx_uart_disable_access_interrupt();
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}
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#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
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static void uart_npcx_rx_refresh_timeout(struct k_work *work)
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{
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struct uart_npcx_data *data =
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CONTAINER_OF(work, struct uart_npcx_data, rx_refresh_timeout_work);
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uart_npcx_pm_policy_state_lock_put(data, UART_PM_POLICY_STATE_RX_FLAG);
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}
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#endif
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/* UART driver registration */
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static const struct uart_driver_api uart_npcx_driver_api = {
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.poll_in = uart_npcx_poll_in,
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.poll_out = uart_npcx_poll_out,
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.err_check = uart_npcx_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_npcx_fifo_fill,
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.fifo_read = uart_npcx_fifo_read,
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.irq_tx_enable = uart_npcx_irq_tx_enable,
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.irq_tx_disable = uart_npcx_irq_tx_disable,
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.irq_tx_ready = uart_npcx_irq_tx_ready,
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.irq_tx_complete = uart_npcx_irq_tx_complete,
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.irq_rx_enable = uart_npcx_irq_rx_enable,
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.irq_rx_disable = uart_npcx_irq_rx_disable,
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.irq_rx_ready = uart_npcx_irq_rx_ready,
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.irq_err_enable = uart_npcx_irq_err_enable,
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.irq_err_disable = uart_npcx_irq_err_disable,
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.irq_is_pending = uart_npcx_irq_is_pending,
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.irq_update = uart_npcx_irq_update,
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.irq_callback_set = uart_npcx_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int uart_npcx_init(const struct device *dev)
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{
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const struct uart_npcx_config *const config = dev->config;
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struct uart_npcx_data *const data = dev->data;
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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struct uart_reg *const inst = config->inst;
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uint32_t uart_rate;
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int ret;
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/* Turn on device clock first and get source clock freq. */
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ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
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if (ret < 0) {
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LOG_ERR("Turn on UART clock fail %d", ret);
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return ret;
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}
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/*
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* If apb2's clock is not 15MHz, we need to find the other optimized
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* values of UPSR and UBAUD for baud rate 115200.
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*/
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ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&config->clk_cfg,
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&uart_rate);
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if (ret < 0) {
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LOG_ERR("Get UART clock rate error %d", ret);
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return ret;
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}
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/* Configure baud rate */
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ret = uart_set_npcx_baud_rate(inst, data->baud_rate, uart_rate);
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if (ret < 0) {
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LOG_ERR("Set baud rate %d with unsupported apb clock %d failed", data->baud_rate,
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uart_rate);
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return ret;
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}
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/*
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* 8-N-1, FIFO enabled. Must be done after setting
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* the divisor for the new divisor to take effect.
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*/
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inst->UFRS = 0x00;
|
|
|
|
/* Initialize UART FIFO if mode is interrupt driven */
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
/* Enable the UART FIFO mode */
|
|
inst->UMDSL |= BIT(NPCX_UMDSL_FIFO_MD);
|
|
|
|
/* Disable all UART tx FIFO interrupts */
|
|
uart_npcx_dis_all_tx_interrupts(dev);
|
|
|
|
/* Clear UART rx FIFO */
|
|
uart_npcx_clear_rx_fifo(dev);
|
|
|
|
/* Configure UART interrupts */
|
|
config->irq_config_func(dev);
|
|
#endif
|
|
|
|
if (IS_ENABLED(CONFIG_PM)) {
|
|
/* Initialize a miwu device input and its callback function */
|
|
npcx_miwu_init_dev_callback(&data->uart_rx_cb, &config->uart_rx_wui,
|
|
uart_npcx_rx_wk_isr, dev);
|
|
npcx_miwu_manage_dev_callback(&data->uart_rx_cb, true);
|
|
/*
|
|
* Configure the UART wake-up event triggered from a falling
|
|
* edge on CR_SIN pin. No need for callback function.
|
|
*/
|
|
npcx_miwu_interrupt_configure(&config->uart_rx_wui, NPCX_MIWU_MODE_EDGE,
|
|
NPCX_MIWU_TRIG_LOW);
|
|
|
|
#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
|
|
k_work_init_delayable(&data->rx_refresh_timeout_work, uart_npcx_rx_refresh_timeout);
|
|
#endif
|
|
}
|
|
|
|
/* Configure pin-mux for uart device */
|
|
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
|
|
if (ret < 0) {
|
|
LOG_ERR("UART pinctrl setup failed (%d)", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst) \
|
|
static void uart_npcx_irq_config_##inst(const struct device *dev)
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst) .irq_config_func = uart_npcx_irq_config_##inst,
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC(inst) \
|
|
static void uart_npcx_irq_config_##inst(const struct device *dev) \
|
|
{ \
|
|
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), uart_npcx_isr, \
|
|
DEVICE_DT_INST_GET(inst), 0); \
|
|
irq_enable(DT_INST_IRQN(inst)); \
|
|
}
|
|
#else
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst)
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst)
|
|
#define NPCX_UART_IRQ_CONFIG_FUNC(inst)
|
|
#endif
|
|
|
|
#define NPCX_UART_INIT(i) \
|
|
NPCX_UART_IRQ_CONFIG_FUNC_DECL(i); \
|
|
\
|
|
PINCTRL_DT_INST_DEFINE(i); \
|
|
\
|
|
static const struct uart_npcx_config uart_npcx_cfg_##i = { \
|
|
.inst = (struct uart_reg *)DT_INST_REG_ADDR(i), \
|
|
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(i), \
|
|
.uart_rx_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, uart_rx), \
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
|
|
NPCX_UART_IRQ_CONFIG_FUNC_INIT(i) \
|
|
}; \
|
|
\
|
|
static struct uart_npcx_data uart_npcx_data_##i = { .baud_rate = DT_INST_PROP( \
|
|
i, current_speed) }; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(i, &uart_npcx_init, NULL, &uart_npcx_data_##i, \
|
|
&uart_npcx_cfg_##i, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
|
|
&uart_npcx_driver_api); \
|
|
\
|
|
NPCX_UART_IRQ_CONFIG_FUNC(i)
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(NPCX_UART_INIT)
|
|
|
|
#define ENABLE_MIWU_CRIN_IRQ(i) \
|
|
npcx_miwu_irq_get_and_clear_pending(&uart_npcx_cfg_##i.uart_rx_wui); \
|
|
npcx_miwu_irq_enable(&uart_npcx_cfg_##i.uart_rx_wui);
|
|
|
|
#define DISABLE_MIWU_CRIN_IRQ(i) npcx_miwu_irq_disable(&uart_npcx_cfg_##i.uart_rx_wui);
|
|
|
|
void npcx_uart_enable_access_interrupt(void)
|
|
{
|
|
DT_INST_FOREACH_STATUS_OKAY(ENABLE_MIWU_CRIN_IRQ)
|
|
}
|
|
|
|
void npcx_uart_disable_access_interrupt(void)
|
|
{
|
|
DT_INST_FOREACH_STATUS_OKAY(DISABLE_MIWU_CRIN_IRQ)
|
|
}
|