208 lines
6.3 KiB
C
208 lines
6.3 KiB
C
/*
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* Copyright 2022, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_mipi_dsi
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#include <zephyr/drivers/mipi_dsi.h>
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#include <fsl_mipi_dsi.h>
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#include <fsl_clock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dsi_mcux, CONFIG_MIPI_DSI_LOG_LEVEL);
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#define MIPI_DPHY_REF_CLK DT_INST_PROP(0, dphy_ref_frequency)
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/*
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* The DPHY bit clock must be fast enough to send out the pixels, it should be
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* larger than:
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*
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* (Pixel clock * bit per output pixel) / number of MIPI data lane
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*
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* Here the desired DPHY bit clock multiplied by ( 9 / 8 = 1.125) to ensure
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* it is fast enough.
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*/
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#define MIPI_DPHY_BIT_CLK_ENLARGE(origin) (((origin) / 8) * 9)
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struct display_mcux_mipi_dsi_config {
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MIPI_DSI_Type base;
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dsi_dpi_config_t dpi_config;
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bool auto_insert_eotp;
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};
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struct display_mcux_mipi_dsi_data {
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const struct device *dev;
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};
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static int dsi_mcux_attach(const struct device *dev,
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uint8_t channel,
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const struct mipi_dsi_device *mdev)
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{
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const struct display_mcux_mipi_dsi_config *config = dev->config;
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dsi_dphy_config_t dphy_config;
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dsi_config_t dsi_config;
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uint32_t mipi_dsi_esc_clk_hz;
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uint32_t mipi_dsi_tx_esc_clk_hz;
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uint32_t mipi_dsi_dphy_ref_clk_hz = MIPI_DPHY_REF_CLK;
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DSI_GetDefaultConfig(&dsi_config);
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dsi_config.numLanes = mdev->data_lanes;
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dsi_config.autoInsertEoTp = config->auto_insert_eotp;
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/* Init the DSI module. */
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DSI_Init((MIPI_DSI_Type *)&config->base, &dsi_config);
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/* Init DPHY.
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*
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* The DPHY bit clock must be fast enough to send out the pixels, it should be
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* larger than:
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*
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* (Pixel clock * bit per output pixel) / number of MIPI data lane
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*
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* Here the desired DPHY bit clock multiplied by ( 9 / 8 = 1.125) to ensure
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* it is fast enough.
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*
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* Note that the DSI output pixel is 24bit per pixel.
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*/
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uint32_t mipi_dsi_dpi_clk_hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Lcdif);
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uint32_t mipi_dsi_dphy_bit_clk_hz = mipi_dsi_dpi_clk_hz * (24 / mdev->data_lanes);
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mipi_dsi_dphy_bit_clk_hz = MIPI_DPHY_BIT_CLK_ENLARGE(mipi_dsi_dphy_bit_clk_hz);
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mipi_dsi_esc_clk_hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Mipi_Esc);
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mipi_dsi_tx_esc_clk_hz = mipi_dsi_esc_clk_hz / 3;
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DSI_GetDphyDefaultConfig(&dphy_config, mipi_dsi_dphy_bit_clk_hz, mipi_dsi_tx_esc_clk_hz);
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mipi_dsi_dphy_bit_clk_hz = DSI_InitDphy((MIPI_DSI_Type *)&config->base,
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&dphy_config, mipi_dsi_dphy_ref_clk_hz);
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/* Init DPI interface. */
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DSI_SetDpiConfig((MIPI_DSI_Type *)&config->base, &config->dpi_config, mdev->data_lanes,
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mipi_dsi_dpi_clk_hz, mipi_dsi_dphy_bit_clk_hz);
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imxrt_post_init_display_interface();
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return 0;
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}
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static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
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struct mipi_dsi_msg *msg)
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{
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const struct display_mcux_mipi_dsi_config *config = dev->config;
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dsi_transfer_t dsi_xfer = {0};
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status_t status;
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dsi_xfer.virtualChannel = channel;
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dsi_xfer.txDataSize = msg->tx_len;
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dsi_xfer.txData = msg->tx_buf;
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dsi_xfer.rxDataSize = msg->rx_len;
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dsi_xfer.rxData = msg->rx_buf;
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switch (msg->type) {
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case MIPI_DSI_DCS_READ:
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LOG_ERR("DCS Read not yet implemented or used");
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return -ENOTSUP;
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case MIPI_DSI_DCS_SHORT_WRITE:
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dsi_xfer.sendDscCmd = true;
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dsi_xfer.dscCmd = msg->cmd;
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dsi_xfer.txDataType = kDSI_TxDataDcsShortWrNoParam;
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break;
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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__fallthrough;
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case MIPI_DSI_DCS_LONG_WRITE:
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dsi_xfer.sendDscCmd = true;
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dsi_xfer.dscCmd = msg->cmd;
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dsi_xfer.txDataType = kDSI_TxDataDcsShortWrOneParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrNoParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrOneParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrTwoParam;
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break;
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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__fallthrough;
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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__fallthrough;
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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LOG_ERR("Generic Read not yet implemented or used");
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return -ENOTSUP;
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default:
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LOG_ERR("Unsupported message type (%d)", msg->type);
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return -ENOTSUP;
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}
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status = DSI_TransferBlocking(&config->base, &dsi_xfer);
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if (status != kStatus_Success) {
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LOG_ERR("Transmission failed");
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return -EIO;
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}
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if (msg->rx_len != 0) {
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/* Return rx_len on a read */
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return msg->rx_len;
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}
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/* Return tx_len on a write */
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return msg->tx_len;
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}
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static struct mipi_dsi_driver_api dsi_mcux_api = {
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.attach = dsi_mcux_attach,
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.transfer = dsi_mcux_transfer,
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};
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static int display_mcux_mipi_dsi_init(const struct device *dev)
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{
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imxrt_pre_init_display_interface();
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return 0;
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}
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#define MCUX_MIPI_DSI_DEVICE(id) \
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static const struct display_mcux_mipi_dsi_config display_mcux_mipi_dsi_config_##id = { \
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.base = { \
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.host = (DSI_HOST_Type *)DT_INST_REG_ADDR_BY_IDX(id, 0), \
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.dpi = (DSI_HOST_DPI_INTFC_Type *)DT_INST_REG_ADDR_BY_IDX(id, 1), \
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.apb = (DSI_HOST_APB_PKT_IF_Type *)DT_INST_REG_ADDR_BY_IDX(id, 2), \
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.dphy = (DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *) \
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DT_INST_REG_ADDR_BY_IDX(id, 3), \
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}, \
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.dpi_config = { \
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.dpiColorCoding = DT_INST_ENUM_IDX(id, dpi_color_coding), \
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.pixelPacket = DT_INST_ENUM_IDX(id, dpi_pixel_packet), \
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.videoMode = DT_INST_ENUM_IDX(id, dpi_video_mode), \
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.bllpMode = DT_INST_ENUM_IDX(id, dpi_bllp_mode), \
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.pixelPayloadSize = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, width), \
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.panelHeight = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, height), \
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.polarityFlags = DT_INST_PROP_BY_PHANDLE_IDX( \
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id, nxp_lcdif, id, polarity) >> 2, \
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.hfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hfp), \
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.hbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hbp), \
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.hsw = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hsync), \
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.vfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vfp), \
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.vbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vbp), \
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}, \
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.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp), \
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}; \
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static struct display_mcux_mipi_dsi_data display_mcux_mipi_dsi_data_##id; \
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DEVICE_DT_INST_DEFINE(id, \
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&display_mcux_mipi_dsi_init, \
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NULL, \
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&display_mcux_mipi_dsi_data_##id, \
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&display_mcux_mipi_dsi_config_##id, \
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POST_KERNEL, \
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CONFIG_MIPI_DSI_INIT_PRIORITY, \
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&dsi_mcux_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_MIPI_DSI_DEVICE)
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