zephyr/drivers/clock_control
Francois Ramu 95c00f4d7a drivers: clock_control: no PLLEN on some stm32 soc
Some stm32 devices, like stm32F4, do not have
a PLL Enable bit on the PLLP nor PLLQ divider
in their PLL config register (PLLCFGR).
The result is a empty function.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-08 10:48:54 +02:00
..
CMakeLists.txt drivers: clock: rcar: Deploy a driver for each soc 2022-06-28 18:11:44 +02:00
Kconfig drivers/clock_control: Add cAVS clock driver 2022-06-27 12:42:04 +02:00
Kconfig.beetle
Kconfig.cavs drivers/clock_control: Add cAVS clock driver 2022-06-27 12:42:04 +02:00
Kconfig.esp32
Kconfig.esp32c3
Kconfig.litex
Kconfig.lpc11u6x
Kconfig.mcux_ccm
Kconfig.mcux_ccm_rev2
Kconfig.mcux_mcg
Kconfig.mcux_pcc
Kconfig.mcux_scg
Kconfig.mcux_sim
Kconfig.mcux_syscon
Kconfig.npcx
Kconfig.nrf drivers: clock_control: Calibration default on if not BOARD_ENABLE_CPUNET 2022-06-06 22:45:44 +02:00
Kconfig.rcar drivers: clock: rcar: Deploy a driver for each soc 2022-06-28 18:11:44 +02:00
Kconfig.rv32m1
Kconfig.stm32
Kconfig.xec
beetle_clock_control.c
clock_agilex.c drivers: clock_control: Use Agile clock sub system as clock id 2022-07-05 15:38:54 +00:00
clock_agilex_ll.c
clock_control_cavs.c drivers/clock_control: Add cAVS clock driver 2022-06-27 12:42:04 +02:00
clock_control_esp32.c
clock_control_esp32c3.c
clock_control_litex.c
clock_control_litex.h
clock_control_lpc11u6x.c drivers: clock_control: convert lpc11u6x syscon driver to pinctrl 2022-05-10 17:27:44 -05:00
clock_control_lpc11u6x.h drivers: clock_control: convert lpc11u6x syscon driver to pinctrl 2022-05-10 17:27:44 -05:00
clock_control_mchp_xec.c
clock_control_mcux_ccm.c I2S_MCUX: Fixup I2S MCUX Audio PLL Rate Calculation and Reg Writes 2022-05-19 11:01:53 -05:00
clock_control_mcux_ccm_rev2.c
clock_control_mcux_mcg.c
clock_control_mcux_pcc.c
clock_control_mcux_scg.c
clock_control_mcux_sim.c drivers: clock_control: mcux_sim: Remove dead code 2022-06-10 09:47:21 +02:00
clock_control_mcux_syscon.c drivers: clock_control: mcux_lpc_syscon_clock: Add flexcomm16 suppport 2022-06-13 12:10:57 +02:00
clock_control_npcx.c drivers: add mising braces to single line if statements 2022-07-06 11:00:45 -04:00
clock_control_nrf.c
clock_control_r8a7795_cpg_mssr.c drivers: clock: rcar: Rename global includes file 2022-06-28 18:11:44 +02:00
clock_control_renesas_cpg_mssr.c drivers: clock: rcar: Rename global includes file 2022-06-28 18:11:44 +02:00
clock_control_renesas_cpg_mssr.h drivers: clock: rcar: Deploy a driver for each soc 2022-06-28 18:11:44 +02:00
clock_control_rv32m1_pcc.c
clock_stm32_ll_common.c drivers: clock_control: no PLLEN on some stm32 soc 2022-07-08 10:48:54 +02:00
clock_stm32_ll_common.h drivers/clock_control: stm32 common allow pll also when it is not sysclk 2022-07-04 16:41:24 +02:00
clock_stm32_ll_h7.c drivers: clock_control: stm32h7: wait for VOS change 2022-06-16 11:26:35 +02:00
clock_stm32_ll_mp1.c
clock_stm32_ll_u5.c drivers/clock_control: stm32u5: Wrong bus check in _get_rate() 2022-05-24 08:51:52 -07:00
clock_stm32_mux.c include: stm32: clock_control: Ease usage of STM32_DT_CLOCKS macro 2022-06-28 11:07:29 +02:00
clock_stm32f0_f3.c drivers/clock_control: stm32 common allow pll also when it is not sysclk 2022-07-04 16:41:24 +02:00
clock_stm32f1.c drivers/clock_control: stm32 common allow pll also when it is not sysclk 2022-07-04 16:41:24 +02:00
clock_stm32f2_f4_f7.c drivers: clock: get_pllsrc_frequency for stm32f2/f4/f7 2022-07-08 10:48:54 +02:00
clock_stm32g0.c drivers/clock_control: stm32 g0, g4, l4, remove get_pllout_frequency() 2022-07-04 16:41:24 +02:00
clock_stm32g4.c drivers/clock_control: stm32 g0, g4, l4, remove get_pllout_frequency() 2022-07-04 16:41:24 +02:00
clock_stm32l0_l1.c drivers/clock_control: stm32 common allow pll also when it is not sysclk 2022-07-04 16:41:24 +02:00
clock_stm32l4_l5_wb_wl.c drivers/clock_control: stm32 g0, g4, l4, remove get_pllout_frequency() 2022-07-04 16:41:24 +02:00
nrf_clock_calibration.c
nrf_clock_calibration.h