337 lines
9.1 KiB
C
337 lines
9.1 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-A, Cortex-M and Cortex-R interrupt management
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*
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*
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* Interrupt management: enabling/disabling and dynamic ISR
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* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
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* connecting ISRs at runtime.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <cmsis_core.h>
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#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
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|| defined(CONFIG_CPU_AARCH32_CORTEX_R)
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#endif
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/irq.h>
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#include <zephyr/tracing/tracing.h>
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#include <zephyr/pm/pm.h>
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extern void z_arm_reserved(void);
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#if defined(CONFIG_CPU_CORTEX_M)
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#define NUM_IRQS_PER_REG 32
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#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
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#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
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void arch_irq_enable(unsigned int irq)
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{
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NVIC_EnableIRQ((IRQn_Type)irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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NVIC_DisableIRQ((IRQn_Type)irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
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}
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/**
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* The priority is verified if ASSERT_ON is enabled. The maximum number
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* of priority levels is a little complex, as there are some hardware
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* priority levels which are reserved.
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*/
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void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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/* The kernel may reserve some of the highest priority levels.
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* So we offset the requested priority level with the number
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* of priority levels reserved by the kernel.
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*/
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/* If we have zero latency interrupts, those interrupts will
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* run at a priority level which is not masked by irq_lock().
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* Our policy is to express priority levels with special properties
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* via flags
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*/
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if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
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if (ZERO_LATENCY_LEVELS == 1) {
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prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
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} else {
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/* Use caller supplied prio level as-is */
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}
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} else {
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prio += _IRQ_PRIO_OFFSET;
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}
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/* The last priority level is also used by PendSV exception, but
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* allow other interrupts to use the same level, even if it ends up
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* affecting performance (can still be useful on systems with a
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* reduced set of priorities, like Cortex-M0/M0+).
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*/
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__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
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"invalid priority %d for %d irq! values must be less than %lu\n",
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prio - _IRQ_PRIO_OFFSET, irq,
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BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
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NVIC_SetPriority((IRQn_Type)irq, prio);
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}
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#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
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|| defined(CONFIG_CPU_AARCH32_CORTEX_R)
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/*
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* For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM
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* Generic Interrupt Controller (GIC) and therefore the architecture interrupt
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* control functions are mapped to the GIC driver interface.
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*
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* When a custom interrupt controller is used (i.e.
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* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
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* interrupt control functions are mapped to the SoC layer in
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* `include/arch/arm/aarch32/irq.h`.
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*/
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#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
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void arch_irq_enable(unsigned int irq)
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{
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arm_gic_irq_enable(irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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arm_gic_irq_disable(irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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return arm_gic_irq_is_enabled(irq);
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}
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/**
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* The priority is verified if ASSERT_ON is enabled. The maximum number
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* of priority levels is a little complex, as there are some hardware
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* priority levels which are reserved: three for various types of exceptions,
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* and possibly one additional to support zero latency interrupts.
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*/
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void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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arm_gic_irq_set_priority(irq, prio, flags);
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}
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#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
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#endif /* CONFIG_CPU_CORTEX_M */
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void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
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/**
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*
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* @brief Spurious interrupt handler
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*
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* Installed in all _sw_isr_table slots at boot time. Throws an error if
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* called.
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*
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*/
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void z_irq_spurious(const void *unused)
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{
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ARG_UNUSED(unused);
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z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
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}
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#ifdef CONFIG_PM
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void _arch_isr_direct_pm(void)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_AARCH32_ARMV8_R) \
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|| defined(CONFIG_ARMV7_A)
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unsigned int key;
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/* irq_lock() does what we want for this CPU */
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key = irq_lock();
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* Lock all interrupts. irq_lock() will on this CPU only disable those
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* lower than BASEPRI, which is not what we want. See comments in
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* arch/arm/core/aarch32/isr_wrapper.S
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*/
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__asm__ volatile("cpsid i" : : : "memory");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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if (_kernel.idle) {
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_kernel.idle = 0;
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z_pm_save_idle_exit();
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}
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_AARCH32_ARMV8_R) \
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|| defined(CONFIG_ARMV7_A)
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irq_unlock(key);
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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__asm__ volatile("cpsie i" : : : "memory");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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#endif
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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/**
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*
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* @brief Set the target security state for the given IRQ
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*
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* Function sets the security state (Secure or Non-Secure) targeted
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* by the given irq. It requires ARMv8-M MCU.
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* It is only compiled if ARM_SECURE_FIRMWARE is defined.
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* It should only be called while in Secure state, otherwise, a write attempt
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* to NVIC.ITNS register is write-ignored(WI), as the ITNS register is not
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* banked between security states and, therefore, has no Non-Secure instance.
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*
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* It shall return the resulting target state of the given IRQ, indicating
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* whether the operation has been performed successfully.
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*
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* @param irq IRQ line
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* @param irq_target_state the desired IRQ target state
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*
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* @return The resulting target state of the given IRQ
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*/
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irq_target_state_t irq_target_state_set(unsigned int irq,
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irq_target_state_t irq_target_state)
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{
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uint32_t result;
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if (irq_target_state == IRQ_TARGET_STATE_SECURE) {
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/* Set target to Secure */
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result = NVIC_ClearTargetState(irq);
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} else {
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/* Set target to Non-Secure */
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result = NVIC_SetTargetState(irq);
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}
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if (result) {
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return IRQ_TARGET_STATE_NON_SECURE;
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} else {
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return IRQ_TARGET_STATE_SECURE;
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}
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}
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/**
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*
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* @brief Determine whether the given IRQ targets the Secure state
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*
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* Function determines whether the given irq targets the Secure state
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* or not (i.e. targets the Non-Secure state). It requires ARMv8-M MCU.
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* It is only compiled if ARM_SECURE_FIRMWARE is defined.
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* It should only be called while in Secure state, otherwise, a read attempt
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* to NVIC.ITNS register is read-as-zero(RAZ), as the ITNS register is not
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* banked between security states and, therefore, has no Non-Secure instance.
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*
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* @param irq IRQ line
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*
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* @return 1 if target state is Secure, 0 otherwise.
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*/
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int irq_target_state_is_secure(unsigned int irq)
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{
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return NVIC_GetTargetState(irq) == 0;
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}
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/**
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*
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* @brief Disable and set all interrupt lines to target Non-Secure state.
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*
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* The function is used to set all HW NVIC interrupt lines to target the
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* Non-Secure state. The function shall only be called fron Secure state.
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*
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* Notes:
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* - All NVIC interrupts are disabled before being routed to Non-Secure.
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* - Bits corresponding to un-implemented interrupts are RES0, so writes
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* will be ignored.
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*
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*/
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void irq_target_state_set_all_non_secure(void)
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{
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int i;
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/* Disable (Clear) all NVIC interrupt lines. */
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for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
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NVIC->ICER[i] = 0xFFFFFFFF;
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}
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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/* Set all NVIC interrupt lines to target Non-Secure */
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for (i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) {
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NVIC->ITNS[i] = 0xFFFFFFFF;
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}
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}
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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#ifdef CONFIG_GEN_ISR_TABLES
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int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
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void (*routine)(const void *parameter),
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const void *parameter, uint32_t flags)
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{
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z_isr_install(irq, routine, parameter);
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z_arm_irq_priority_set(irq, priority, flags);
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return irq;
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}
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#endif /* CONFIG_GEN_ISR_TABLES */
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#ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS
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static inline void z_arm_irq_dynamic_direct_isr_dispatch(void)
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{
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uint32_t irq = __get_IPSR() - 16;
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if (irq < IRQ_TABLE_SIZE) {
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struct _isr_table_entry *isr_entry = &_sw_isr_table[irq];
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isr_entry->isr(isr_entry->arg);
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}
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}
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ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule)
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{
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z_arm_irq_dynamic_direct_isr_dispatch();
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return 1;
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}
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ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule)
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{
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z_arm_irq_dynamic_direct_isr_dispatch();
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return 0;
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}
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#endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */
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#endif /* CONFIG_DYNAMIC_INTERRUPTS */
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