zephyr/dts/bindings/cpu
Daniel Leung 78837c769a soc: x86: add Lakemont SoC
This adds a very basic SoC configuration for Intel Lakemont SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-19 18:51:04 -05:00
..
altr,nios2f.yaml
arm,cortex-a53.yaml
arm,cortex-a72.yaml
arm,cortex-m0+.yaml
arm,cortex-m0.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml dts: bindings: Add CPU device bindings for Cortex-R7. 2021-01-13 15:04:43 +01:00
cadence,tensilica-xtensa-lx4.yaml
cadence,tensilica-xtensa-lx6.yaml
cpu.yaml dts: bindings: Remove defaults for cache lines from cpu binding 2021-02-03 13:41:47 -05:00
intel,apollo_lake.yaml dts/bindings: Fixing x86 CPU compatibles by providing proper yaml files 2021-02-15 09:43:30 -05:00
intel,atom.yaml dts/bindings: Fixing x86 CPU compatibles by providing proper yaml files 2021-02-15 09:43:30 -05:00
intel,elkhart_lake.yaml dts/bindings: Fixing x86 CPU compatibles by providing proper yaml files 2021-02-15 09:43:30 -05:00
intel,lakemont.yml soc: x86: add Lakemont SoC 2021-02-19 18:51:04 -05:00
intel,x86.yaml dts/bindings: Fixing x86 CPU compatibles by providing proper yaml files 2021-02-15 09:43:30 -05:00
qemu,nios2-zephyr.yaml
riscv,it8xxx2.yaml dts: it8xxx2 device tree and binding 2020-12-16 08:47:36 -05:00
sample_controller.yaml
snps,arcem.yaml