156 lines
4.2 KiB
C
156 lines
4.2 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_cavs_intc
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/irq.h>
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#include <zephyr/irq_nextlevel.h>
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#include <zephyr/sys/arch_interface.h>
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#include "intc_cavs.h"
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#if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
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#if defined(CONFIG_SOC_INTEL_CAVS_V25)
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#define PER_CPU_OFFSET(x) (0x40 * x)
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#else
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#error "Must define PER_CPU_OFFSET(x) for SoC"
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#endif
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#else
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#define PER_CPU_OFFSET(x) 0
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#endif
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static ALWAYS_INLINE
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struct cavs_registers *get_base_address(struct cavs_ictl_runtime *context)
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{
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#if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
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return UINT_TO_POINTER(context->base_addr +
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PER_CPU_OFFSET(arch_curr_cpu()->id));
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#else
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return UINT_TO_POINTER(context->base_addr);
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#endif
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}
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static ALWAYS_INLINE void cavs_ictl_dispatch_child_isrs(uint32_t intr_status,
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uint32_t isr_base_offset)
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{
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uint32_t intr_bitpos, intr_offset;
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/* Dispatch lower level ISRs depending upon the bit set */
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while (intr_status) {
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intr_bitpos = find_lsb_set(intr_status) - 1;
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intr_status &= ~(1 << intr_bitpos);
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intr_offset = isr_base_offset + intr_bitpos;
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_sw_isr_table[intr_offset].isr(
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_sw_isr_table[intr_offset].arg);
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}
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}
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static void cavs_ictl_isr(const struct device *port)
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{
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struct cavs_ictl_runtime *context = port->data;
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const struct cavs_ictl_config *config = port->config;
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volatile struct cavs_registers * const regs = get_base_address(context);
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cavs_ictl_dispatch_child_isrs(regs->status_il,
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config->isr_table_offset);
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}
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static void cavs_ictl_irq_enable(const struct device *dev,
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unsigned int irq)
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{
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struct cavs_ictl_runtime *context = dev->data;
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volatile struct cavs_registers * const regs = get_base_address(context);
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regs->enable_il = 1 << irq;
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}
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static void cavs_ictl_irq_disable(const struct device *dev,
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unsigned int irq)
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{
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struct cavs_ictl_runtime *context = dev->data;
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volatile struct cavs_registers * const regs = get_base_address(context);
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regs->disable_il = 1 << irq;
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}
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static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
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{
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struct cavs_ictl_runtime *context = dev->data;
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volatile struct cavs_registers * const regs = get_base_address(context);
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/* When the bits of this register are set, it means the
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* corresponding interrupts are disabled. This function
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* returns 0 only if ALL the interrupts are disabled.
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*/
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return regs->disable_state_il != 0xFFFFFFFF;
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}
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static int cavs_ictl_irq_get_line_state(const struct device *dev,
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unsigned int irq)
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{
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struct cavs_ictl_runtime *context = dev->data;
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volatile struct cavs_registers * const regs = get_base_address(context);
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if ((regs->disable_state_il & BIT(irq)) == 0) {
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return 1;
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}
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return 0;
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}
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static const struct irq_next_level_api cavs_apis = {
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.intr_enable = cavs_ictl_irq_enable,
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.intr_disable = cavs_ictl_irq_disable,
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.intr_get_state = cavs_ictl_irq_get_state,
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.intr_get_line_state = cavs_ictl_irq_get_line_state,
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};
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#define CAVS_ICTL_INIT(n) \
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static int cavs_ictl_##n##_initialize(const struct device *port) \
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{ \
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struct cavs_ictl_runtime *context = port->data; \
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volatile struct cavs_registers * const regs = \
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get_base_address(context); \
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regs->disable_il = ~0; \
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\
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return 0; \
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} \
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\
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static void cavs_config_##n##_irq(const struct device *port); \
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\
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static const struct cavs_ictl_config cavs_config_##n = { \
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.irq_num = DT_INST_IRQN(n), \
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.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + \
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CONFIG_MAX_IRQ_PER_AGGREGATOR*n, \
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.config_func = cavs_config_##n##_irq, \
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}; \
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\
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static struct cavs_ictl_runtime cavs_##n##_runtime = { \
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.base_addr = DT_INST_REG_ADDR(n), \
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}; \
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DEVICE_DT_INST_DEFINE(n, \
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cavs_ictl_##n##_initialize, \
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NULL, \
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&cavs_##n##_runtime, &cavs_config_##n, \
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PRE_KERNEL_1, \
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CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);\
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\
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static void cavs_config_##n##_irq(const struct device *port) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
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cavs_ictl_isr, DEVICE_DT_INST_GET(n), \
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DT_INST_IRQ(n, sense)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(CAVS_ICTL_INIT)
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