Keith Packard f623571a73 riscv: Initialize TP register when starting threads ... Set TP in exception context so that it gets loaded into the CPU when first running the thread. Set TP for secondary cores to related idle TLS area. Signed-off-by: Keith Packard <keithp@keithp.com>		2022-04-28 11:09:01 +09:00
..
arc	everywhere: fix typos	2022-03-18 13:24:08 -04:00
arm	arch/arm: Use TPIDRURO on cortex-a too	2022-04-28 11:09:01 +09:00
arm64	semihosting: fix inline assembly output dependency	2022-04-24 19:46:15 +02:00
common	arch: common: semihost: add semihosting operations	2022-04-21 13:04:52 +02:00
mips	kconfig: Rename the TEST_EXTRA stack size option to align with the rest	2022-02-22 08:23:05 -05:00
nios2	core: z_data_copy does not depend on CONFIG_XIP	2022-02-22 10:22:53 +01:00
posix	debug: generate call graph profile data using gprof	2022-04-22 16:04:08 -04:00
riscv	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
sparc	everywhere: fix typos	2022-03-18 13:24:08 -04:00
x86	x86: Initialise FPU regs during thread creation for eager FPU sharing	2022-04-18 17:23:48 -07:00
xtensa	arch/xtensa: Optimize cache management on context switch	2022-04-27 18:54:10 -04:00
CMakeLists.txt	…
Kconfig	arch/arm: Use TPIDRURO on cortex-a too	2022-04-28 11:09:01 +09:00