zephyr/soc/riscv
Kevin Wang 25b4bd186d soc: riscv: riscv-privilege: andes_v5: ae350: MP_NUM_CPUS default value
Overlay zephyr kernel MP_NUM_CPUS from 1-8 (default 1-4)
for supporting 8 cpu cores.

Signed-off-by: Kevin Wang <yunkai@andestech.com>
2022-08-03 05:00:14 +01:00
..
esp32c3 esp32c3: Avoid circular header inclusion 2022-07-07 10:00:20 +02:00
litex-vexriscv soc: riscv: remove unused RISCV_RAM_BASE|SIZE definitions 2022-07-28 20:51:31 +02:00
openisa_rv32m1 i2c: remove Kconfig.defconfig setting of I2C drivers 2022-08-01 18:01:44 +02:00
riscv-ite adc: remove Kconfig.defconfig setting of ADC drivers 2022-08-02 15:51:43 -05:00
riscv-privilege soc: riscv: riscv-privilege: andes_v5: ae350: MP_NUM_CPUS default value 2022-08-03 05:00:14 +01:00
CMakeLists.txt