8b24346bff
llvm will generate a different div instruction than gcc does and than the number of types that the div instruction opcode takes is not 2. Move to using inline asm with a idivl instruction to ensure the opcode size is what we expect so that exc_divide_error_handler() can properly skip over the instruction. Signed-off-by: Kumar Gala <kumar.gala@intel.com> |
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| arc/arc_dsp_sharing | ||
| arm | ||
| arm64 | ||
| common | ||
| riscv/fpu_sharing | ||
| x86 | ||