103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/* spi_intel.h - Intel's SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_
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#define ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_
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#include "spi_intel_regs.h"
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#include "spi_context.h"
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#ifdef CONFIG_PCI
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#include <pci/pci.h>
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#include <pci/pci_mgr.h>
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#endif /* CONFIG_PCI */
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*spi_intel_config_t)(void);
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struct spi_intel_config {
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u32_t irq;
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spi_intel_config_t config_func;
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};
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struct spi_intel_data {
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struct spi_context ctx;
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u32_t regs;
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#ifdef CONFIG_PCI
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struct pci_dev_info pci_dev;
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#endif /* CONFIG_PCI */
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u32_t sscr0;
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u32_t sscr1;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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#endif
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u8_t dfs;
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};
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#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
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static inline u32_t read_##__reg(u32_t addr) \
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{ \
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return sys_read##__sz(addr + __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
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static inline void write_##__reg(u32_t data, u32_t addr) \
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{ \
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sys_write##__sz(data, addr + __off); \
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}
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DEFINE_MM_REG_WRITE(sscr0, INTEL_SPI_REG_SSCR0, 32)
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DEFINE_MM_REG_WRITE(sscr1, INTEL_SPI_REG_SSCR1, 32)
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DEFINE_MM_REG_READ(sssr, INTEL_SPI_REG_SSSR, 32)
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DEFINE_MM_REG_READ(ssdr, INTEL_SPI_REG_SSDR, 32)
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DEFINE_MM_REG_WRITE(ssdr, INTEL_SPI_REG_SSDR, 32)
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DEFINE_MM_REG_WRITE(dds_rate, INTEL_SPI_REG_DDS_RATE, 32)
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#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void set_bit_##__reg_bit(u32_t addr) \
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{ \
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sys_set_bit(addr + __reg_off, __bit); \
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}
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#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void clear_bit_##__reg_bit(u32_t addr) \
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{ \
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sys_clear_bit(addr + __reg_off, __bit); \
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}
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#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline int test_bit_##__reg_bit(u32_t addr) \
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{ \
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return sys_test_bit(addr + __reg_off, __bit); \
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}
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DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
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DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
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DEFINE_TEST_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
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DEFINE_CLEAR_BIT_OP(sssr_ror, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_ROR_BIT)
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/* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
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* These are the bits were when you divide by 8, you keep the result as it is.
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* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
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* since on such division it takes only the result above 0
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*/
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#define SPI_WS_TO_DFS(__bpw) (((__bpw) & ~0x38) ? \
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(((__bpw) / 8) + 1) : \
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((__bpw) / 8))
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_ */
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