zephyr/dts/arm/nordic/nrf51822.dtsi

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#include <arm/armv6-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <nordic/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0";
reg = <0>;
};
};
flash-controller@4001E000 {
compatible = "nrf,nrf51-flash-controller";
reg = <0x4001E000 0x518>;
#address-cells = <1>;
#size-cells = <1>;
label="NRF_FLASH_DRV_NAME";
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "NRF_FLASH";
reg = <0x00000000 DT_FLASH_SIZE>;
write-block-size = <4>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
uart0: uart@40002000 {
compatible = "nordic,nrf-uart";
reg = <0x40002000 0x1000>;
interrupts = <2 1>;
status = "disabled";
label = "UART_0";
};
i2c0: i2c@40003000 {
compatible = "nordic,nrf5-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <3 1>;
status = "disabled";
label = "I2C_0";
};
i2c1: i2c@40004000 {
compatible = "nordic,nrf5-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40004000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <4 1>;
status = "disabled";
label = "I2C_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};