197 lines
6.1 KiB
ReStructuredText
197 lines
6.1 KiB
ReStructuredText
.. _xt-sim:
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Xtensa simulator
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################
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Overview
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********
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The Xtensa processor architecture is a configurable, extensible, and
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synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
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from various processor options and even create customized instructions in
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addition to a base ISA to tailor the processor for a particular application.
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For more information, see https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
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Zephyr applications use the xt-sim configuration to run on the Xtensa simulator
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emulating Xtensa hardware.
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.. figure:: img/Xplorer-splash.png
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:width: 612px
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:align: center
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:alt: Xtensa Xplorer (Eclipse base frontend for xt-sim)
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Xtensa Xplorer
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Hardware
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********
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The folllowing Xtensa cores are officially supported:
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- hifi3_bd5
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- XRC_FUSION_AON_ALL_LM
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- D_108mini
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- D_212GP
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- D_233L
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- hifi_mini_4swIrq (call0 ABI, added 4 SW IRQ for tests and 1 timer level 1)
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- hifi2_std
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- XRC_D2PM_5swIrq (added 4 SW IRQ for tests and 1 timer level 1)
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- hifi4_bd7 (Big Endian)
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- hifi3_bd5_call0 (call0 ABI, added 3 SW IRQs for tests)
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System Clock
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============
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Xtensa cores can be configured to use either internal or external timers.
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The frequency of the clock under simulation is set to 25MHz.
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System requirements
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*******************
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Prerequisites
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=============
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A Linux host system is required for Xtensa development work.
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We recommend using a __``Debian 9.x (Stretch)``__ or recent __``Ubuntu``__
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releases (with multilib support).
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Only `Xtensa tools` version ``RF-2016.4-linux`` or later are officially
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supported. Other versions may work but are not supported by Cadence Systems Inc.
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In order to set up the Zephyr OS build system, a Linux 32-bit GCC compiler must
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be installed on the building linux box. Install GCC if needed either by
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downloading ``Zephyr SDK`` or by using your distribution package manager.
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On Debian/Ubuntu systems, you can install ``gcc-multilib`` package as follows:
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.. code-block:: console
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#aptitude install gcc-multilib # Or what ever package manager (apt, apt-get, ...)
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Set up build environment
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========================
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We recommend you create a ``~/.zephyrrc`` file, a shell script that shall be
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sourced each time before you start working on Zephyr.
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You can use the following code to create that file:
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.. code-block:: console
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$ cat > ~/.zephyrrc
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if test "${CROSS}" = xcc
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then
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export ARCH=xtensa
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export BOARD=xt-sim
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export ZEPHYR_GCC_VARIANT=xcc
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export XTENSA_TOOLS_PATH=/opt/xtensa/XtDevTools/install/tools/RG-2016.4-linux/XtensaTools
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export XTENSA_BUILDS_PATH=/opt/xtensa/XtDevTools/install/builds/RG-2016.4-linux
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#export XTENSA_BUILD_DIR= #Keep empty to use default directory
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export EMU_PLATFORM=xt-run
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elif test "${CROSS}" = zephyr-xtensa
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then
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export ARCH=xtensa
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export BOARD=qemu
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export ZEPHYR_GCC_VARIANT=zephyr
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export ZEPHYR_SDK_INSTALL_DIR=/opt/xtensa/zephyr-sdk-64-INTERNAL-11-22-2016
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elif test "${CROSS}" = zephyr-x86
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then
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export ARCH=x86
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export BOARD=qemu_x86
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export ZEPHYR_GCC_VARIANT=zephyr
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export ZEPHYR_SDK_INSTALL_DIR=/opt/xtensa/zephyr-sdk-64-INTERNAL-11-22-2016
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else
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echo "Unsupported compiler '${CROSS}' defined by environment variable CROSS"
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fi
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Once the ``~/.zephyrrc`` file is created, you can start working. However, each
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time you start a new shell you will need to execute the following commands
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before you can compile anything:
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.. code-block:: console
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$ cd path/to/zephyr # replace path/to by a real path
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$ CROSS=xcc source zephyr-env.sh # Select xcc as compiler
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Adding a user-defined Xtensa core
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=================================
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Add your own core to the list of supported cores as follows:
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.. code-block:: console
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$ XTENSA_CORE=myCore
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$ $(which echo) -e "config ${XTENSA_CORE}\n\tbool \"${XTENSA_CORE} core\"\n" >> "arch/xtensa/soc/Kconfig.cores"
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Create a folder for that core:
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.. code-block:: console
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$ mkdir arch/xtensa/soc/${XTENSA_CORE}
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Create and copy to that folder a custom linker script (more on linker script in next section):
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.. code-block:: console
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$ cp linker.ld arch/xtensa/soc/${XTENSA_CORE}/linker.ld
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Add a Makefile:
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.. code-block:: console
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$ echo "obj-y = soc.o" > arch/xtensa/soc/${XTENSA_CORE}/Makefile
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Add Zephyr specific sections to the linker script.
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The file "arch/xtensa/soc/linker_more.ld" contains Zephyr-specific linker
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sections that should be added to the default linker script linker.ld (inside
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SECTIONS region). If you are not using a linker script, you must create one
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and add these sections. The memory segment and PHDR should be replaced by
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appropriate values. See :file:`arch/xtensa/soc/hifi3_bd5/linker.ld` for an example.
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The linker script should be named ``linker.ld`` and placed in the directory
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``arch/xtensa/soc/${XTENSA_CORE}``.
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Configuring build
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=================
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.. code-block:: console
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$ cd tests/kernel/test_build
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$ make menuconfig
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Below is an example of usage for typical configuration:
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1. Select ``Architecture``
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a. Select ``Xtensa architecture``
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2. Select ``XTENSA core Selection``
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a. Select appropriate core (example ``hifi3_bd5 core``)
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3. Select ``XTENSA Options``
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a. Set ``Hardware clock cycles per second`` to appropriate value
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b. Set ``The path to Xtensa tool`` to appropriate value
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c. Set ``The version of Xtensa tool`` to appropriate version
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d. Set ``Xtensa build directory`` to appropriate value
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4. Select ``Board Selection``
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a. Select ``Xtensa Development ISS``
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5. Select ``Device Drivers``
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a. Uncheck ``Serial Drivers``
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6. Select ``Compile and Link Features``
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a. Set compiler configuration and build options correctly to project requirements
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7. Hit ``Exit`` and confirm saving the changes.
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You may need to change other options in menuconfig depending on his project
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specific needs.
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Compiling and running
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=====================
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The Xtensa executable can be run in the simulator either with a standalone core,
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or with a core connected to simulated peripherals.
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Use make to build and run as follows:
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.. code-block:: console
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$ make run
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References
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**********
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.. _Xtensa tools: https://ip.cadence.com/support/sdk-evaluation-request
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