46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SIFIVE_FU540_PRCI_H
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#define _SIFIVE_FU540_PRCI_H
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x10000000UL
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#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
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/* Register offsets */
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#define PRCI_HFXOSCCFG (0x0000)
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#define PRCI_COREPLLCFG0 (0x0004)
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#define PRCI_DDRPLLCFG0 (0x000c)
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#define PRCI_DDRPLLCFG1 (0x0010)
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#define PRCI_GEMGXLPLLCFG0 (0x001c)
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#define PRCI_GEMGXLPLLCFG1 (0x0020)
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#define PRCI_CORECLKSEL (0x0024)
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#define PRCI_DEVICESRESETREG (0x0028)
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#define PLL_R(x) (((x) & 0x3f) << 0)
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#define PLL_F(x) (((x) & 0x1ff) << 6)
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#define PLL_Q(x) (((x) & 0x7) << 15)
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#define PLL_RANGE(x) (((x) & 0x7) << 18)
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#define PLL_BYPASS(x) (((x) & 0x1) << 24)
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#define PLL_FSE(x) (((x) & 0x1) << 25)
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#define PLL_LOCK(x) (((x) & 0x1) << 31)
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#define PLL_RANGE_33MHZ 4
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#define PLL_BYPASS_DISABLE 0
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#define PLL_BYPASS_ENABLE 1
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#define PLL_FSE_INTERNAL 1
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#define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0)
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#define CORECLKSEL_CORE_PLL 0
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#define CORECLKSEL_HFCLK 1
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#endif /* _SIFIVE_FU540_PRCI_H */
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