60 lines
1016 B
Plaintext
60 lines
1016 B
Plaintext
/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <st/mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash0: flash {
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reg = <0x08000000 DT_FLASH_SIZE>;
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};
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sram0: memory {
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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