377 lines
8.2 KiB
C
377 lines
8.2 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <flash.h>
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#include <spi.h>
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#include <init.h>
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#include <string.h>
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#include "spi_flash_w25qxxdv_defs.h"
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#include "spi_flash_w25qxxdv.h"
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static inline int spi_flash_wb_id(struct device *dev)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t buf[W25QXXDV_LEN_CMD_AND_ID];
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u32_t temp_data;
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buf[0] = W25QXXDV_CMD_RDID;
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if (spi_transceive(driver_data->spi, buf, W25QXXDV_LEN_CMD_AND_ID,
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buf, W25QXXDV_LEN_CMD_AND_ID) != 0) {
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return -EIO;
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}
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temp_data = ((u32_t) buf[1]) << 16;
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temp_data |= ((u32_t) buf[2]) << 8;
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temp_data |= (u32_t) buf[3];
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if (temp_data != W25QXXDV_RDID_VALUE) {
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return -ENODEV;
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}
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return 0;
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}
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static int spi_flash_wb_config(struct device *dev)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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struct spi_config config;
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config.max_sys_freq = CONFIG_SPI_FLASH_W25QXXDV_SPI_FREQ_0;
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config.config = SPI_WORD(8);
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if (spi_slave_select(driver_data->spi,
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CONFIG_SPI_FLASH_W25QXXDV_SPI_SLAVE) !=
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0) {
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return -EIO;
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}
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if (spi_configure(driver_data->spi, &config) != 0) {
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return -EIO;
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}
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return spi_flash_wb_id(dev);
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}
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static int spi_flash_wb_reg_read(struct device *dev, u8_t *data)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t buf[2];
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if (spi_transceive(driver_data->spi, data, 2, buf, 2) != 0) {
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return -EIO;
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}
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memcpy(data, buf, 2);
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return 0;
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}
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static inline void wait_for_flash_idle(struct device *dev)
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{
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u8_t buf[2];
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buf[0] = W25QXXDV_CMD_RDSR;
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spi_flash_wb_reg_read(dev, buf);
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while (buf[1] & W25QXXDV_WIP_BIT) {
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buf[0] = W25QXXDV_CMD_RDSR;
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spi_flash_wb_reg_read(dev, buf);
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}
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}
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static int spi_flash_wb_reg_write(struct device *dev, u8_t *data)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t buf;
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wait_for_flash_idle(dev);
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if (spi_transceive(driver_data->spi, data, 1,
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&buf /*dummy */, 1) != 0) {
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return -EIO;
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}
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return 0;
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}
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static int spi_flash_wb_read(struct device *dev, off_t offset, void *data,
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size_t len)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t *buf = driver_data->buf;
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if (len > CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN || offset < 0) {
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return -ENODEV;
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}
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k_sem_take(&driver_data->sem, K_FOREVER);
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if (spi_flash_wb_config(dev) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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wait_for_flash_idle(dev);
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buf[0] = W25QXXDV_CMD_READ;
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buf[1] = (u8_t) (offset >> 16);
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buf[2] = (u8_t) (offset >> 8);
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buf[3] = (u8_t) offset;
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memset(buf + W25QXXDV_LEN_CMD_ADDRESS, 0, len);
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if (spi_transceive(driver_data->spi, buf, len + W25QXXDV_LEN_CMD_ADDRESS,
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buf, len + W25QXXDV_LEN_CMD_ADDRESS) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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memcpy(data, buf + W25QXXDV_LEN_CMD_ADDRESS, len);
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k_sem_give(&driver_data->sem);
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return 0;
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}
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static int spi_flash_wb_write(struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t *buf = driver_data->buf;
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if (len > CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN || offset < 0) {
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return -ENOTSUP;
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}
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k_sem_take(&driver_data->sem, K_FOREVER);
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if (spi_flash_wb_config(dev) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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wait_for_flash_idle(dev);
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buf[0] = W25QXXDV_CMD_RDSR;
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spi_flash_wb_reg_read(dev, buf);
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if (!(buf[1] & W25QXXDV_WEL_BIT)) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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wait_for_flash_idle(dev);
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buf[0] = W25QXXDV_CMD_PP;
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buf[1] = (u8_t) (offset >> 16);
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buf[2] = (u8_t) (offset >> 8);
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buf[3] = (u8_t) offset;
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memcpy(buf + W25QXXDV_LEN_CMD_ADDRESS, data, len);
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/* Assume write protection has been disabled. Note that w25qxxdv
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* flash automatically turns on write protection at the completion
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* of each write or erase transaction.
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*/
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if (spi_write(driver_data->spi, buf, len + W25QXXDV_LEN_CMD_ADDRESS) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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k_sem_give(&driver_data->sem);
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return 0;
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}
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static int spi_flash_wb_write_protection_set(struct device *dev, bool enable)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t buf = 0;
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k_sem_take(&driver_data->sem, K_FOREVER);
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if (spi_flash_wb_config(dev) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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wait_for_flash_idle(dev);
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if (enable) {
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buf = W25QXXDV_CMD_WRDI;
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} else {
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buf = W25QXXDV_CMD_WREN;
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}
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if (spi_flash_wb_reg_write(dev, &buf) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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k_sem_give(&driver_data->sem);
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return 0;
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}
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static inline int spi_flash_wb_erase_internal(struct device *dev,
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off_t offset, size_t size)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t buf[W25QXXDV_LEN_CMD_ADDRESS];
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u8_t erase_opcode;
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u32_t len;
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if (offset < 0) {
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return -ENOTSUP;
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}
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wait_for_flash_idle(dev);
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/* write enable */
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buf[0] = W25QXXDV_CMD_WREN;
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spi_flash_wb_reg_write(dev, buf);
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wait_for_flash_idle(dev);
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switch (size) {
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case W25QXXDV_SECTOR_SIZE:
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erase_opcode = W25QXXDV_CMD_SE;
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len = W25QXXDV_LEN_CMD_ADDRESS;
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break;
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case W25QXXDV_BLOCK32K_SIZE:
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erase_opcode = W25QXXDV_CMD_BE32K;
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len = W25QXXDV_LEN_CMD_ADDRESS;
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break;
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case W25QXXDV_BLOCK_SIZE:
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erase_opcode = W25QXXDV_CMD_BE;
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len = W25QXXDV_LEN_CMD_ADDRESS;
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break;
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case CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE:
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erase_opcode = W25QXXDV_CMD_CE;
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len = 1;
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break;
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default:
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return -EIO;
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}
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buf[0] = erase_opcode;
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buf[1] = (u8_t) (offset >> 16);
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buf[2] = (u8_t) (offset >> 8);
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buf[3] = (u8_t) offset;
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/* Assume write protection has been disabled. Note that w25qxxdv
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* flash automatically turns on write protection at the completion
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* of each write or erase transaction.
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*/
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return spi_write(driver_data->spi, buf, len);
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}
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static int spi_flash_wb_erase(struct device *dev, off_t offset, size_t size)
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{
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struct spi_flash_data *const driver_data = dev->driver_data;
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u8_t *buf = driver_data->buf;
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int ret = 0;
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u32_t new_offset = offset;
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u32_t size_remaining = size;
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if ((offset < 0) || ((offset & W25QXXDV_SECTOR_MASK) != 0) ||
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((size + offset) > CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE) ||
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((size & W25QXXDV_SECTOR_MASK) != 0)) {
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return -ENODEV;
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}
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k_sem_take(&driver_data->sem, K_FOREVER);
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if (spi_flash_wb_config(dev) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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buf[0] = W25QXXDV_CMD_RDSR;
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spi_flash_wb_reg_read(dev, buf);
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if (!(buf[1] & W25QXXDV_WEL_BIT)) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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while ((size_remaining >= W25QXXDV_SECTOR_SIZE) && (ret == 0)) {
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if (size_remaining == CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE) {
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ret = spi_flash_wb_erase_internal(dev, offset, size);
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break;
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}
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if (size_remaining >= W25QXXDV_BLOCK_SIZE) {
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ret = spi_flash_wb_erase_internal(dev, new_offset,
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W25QXXDV_BLOCK_SIZE);
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new_offset += W25QXXDV_BLOCK_SIZE;
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size_remaining -= W25QXXDV_BLOCK_SIZE;
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continue;
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}
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if (size_remaining >= W25QXXDV_BLOCK32K_SIZE) {
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ret = spi_flash_wb_erase_internal(dev, new_offset,
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W25QXXDV_BLOCK32K_SIZE);
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new_offset += W25QXXDV_BLOCK32K_SIZE;
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size_remaining -= W25QXXDV_BLOCK32K_SIZE;
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continue;
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}
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if (size_remaining >= W25QXXDV_SECTOR_SIZE) {
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ret = spi_flash_wb_erase_internal(dev, new_offset,
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W25QXXDV_SECTOR_SIZE);
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new_offset += W25QXXDV_SECTOR_SIZE;
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size_remaining -= W25QXXDV_SECTOR_SIZE;
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continue;
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}
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}
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k_sem_give(&driver_data->sem);
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return ret;
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}
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static const struct flash_driver_api spi_flash_api = {
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.read = spi_flash_wb_read,
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.write = spi_flash_wb_write,
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.erase = spi_flash_wb_erase,
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.write_protection = spi_flash_wb_write_protection_set,
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};
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static int spi_flash_init(struct device *dev)
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{
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struct device *spi_dev;
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struct spi_flash_data *data = dev->driver_data;
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int ret;
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spi_dev = device_get_binding(CONFIG_SPI_FLASH_W25QXXDV_SPI_NAME);
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if (!spi_dev) {
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return -EIO;
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}
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data->spi = spi_dev;
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k_sem_init(&data->sem, 1, UINT_MAX);
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ret = spi_flash_wb_config(dev);
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if (!ret) {
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dev->driver_api = &spi_flash_api;
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}
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return ret;
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}
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static struct spi_flash_data spi_flash_memory_data;
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DEVICE_INIT(spi_flash_memory, CONFIG_SPI_FLASH_W25QXXDV_DRV_NAME, spi_flash_init,
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&spi_flash_memory_data, NULL, POST_KERNEL,
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CONFIG_SPI_FLASH_W25QXXDV_INIT_PRIORITY);
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