177 lines
4.2 KiB
C
177 lines
4.2 KiB
C
/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_CACHE_H_
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#define ZEPHYR_INCLUDE_CACHE_H_
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#include <kernel.h>
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#include <kernel_structs.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Common operations for the caches
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*
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* WB means write-back and intends to transfer dirty cache lines to memory in a
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* copy-back cache policy. May be a no-op in write-back cache policy.
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*
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* INVD means invalidate and will mark cache lines as not valid. A future
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* access to the associated address is guaranteed to generate a memory fetch.
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*/
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#define K_CACHE_WB BIT(0)
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#define K_CACHE_INVD BIT(1)
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#define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
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#if defined(CONFIG_HAS_EXTERNAL_CACHE)
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/* Driver interface mirrored in include/drivers/cache.h */
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/* Enable d-cache */
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extern void cache_data_enable(void);
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/* Disable d-cache */
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extern void cache_data_disable(void);
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/* Enable i-cache */
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extern void cache_instr_enable(void);
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/* Disable i-cache */
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extern void cache_instr_disable(void);
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/* Write-back / Invalidate / Write-back + Invalidate all d-cache */
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extern int cache_data_all(int op);
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/* Write-back / Invalidate / Write-back + Invalidate d-cache lines */
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extern int cache_data_range(void *addr, size_t size, int op);
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/* Write-back / Invalidate / Write-back + Invalidate all i-cache */
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extern int cache_instr_all(int op);
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/* Write-back / Invalidate / Write-back + Invalidate i-cache lines */
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extern int cache_instr_range(void *addr, size_t size, int op);
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#else
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/* Hooks into arch code */
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#define cache_data_enable arch_dcache_enable
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#define cache_data_disable arch_dcache_disable
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#define cache_instr_enable arch_icache_enable
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#define cache_instr_disable arch_icache_disable
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#define cache_data_all(op) arch_dcache_all(op)
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#define cache_data_range(addr, size, op) arch_dcache_range(addr, size, op)
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#define cache_instr_all(op) arch_icache_all(op)
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#define cache_instr_range(addr, size, op) arch_icache_range(addr, size, op)
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#define cache_data_line_size_get arch_dcache_line_size_get
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#define cache_instr_line_size_get arch_icache_line_size_get
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#endif
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__syscall int sys_cache_data_all(int op);
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static inline int z_impl_sys_cache_data_all(int op)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT)
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return cache_data_all(op);
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#endif
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ARG_UNUSED(op);
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return -ENOTSUP;
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}
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__syscall int sys_cache_data_range(void *addr, size_t size, int op);
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static inline int z_impl_sys_cache_data_range(void *addr, size_t size, int op)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT)
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return cache_data_range(addr, size, op);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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ARG_UNUSED(op);
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return -ENOTSUP;
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}
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__syscall int sys_cache_instr_all(int op);
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static inline int z_impl_sys_cache_instr_all(int op)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT)
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return cache_instr_all(op);
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#endif
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ARG_UNUSED(op);
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return -ENOTSUP;
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}
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__syscall int sys_cache_instr_range(void *addr, size_t size, int op);
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static inline int z_impl_sys_cache_instr_range(void *addr, size_t size, int op)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT)
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return cache_instr_range(addr, size, op);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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ARG_UNUSED(op);
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return -ENOTSUP;
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}
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#ifdef CONFIG_LIBMETAL
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static inline void sys_cache_flush(void *addr, size_t size)
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{
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sys_cache_data_range(addr, size, K_CACHE_WB);
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}
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#endif
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#define CPU DT_PATH(cpus, cpu_0)
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/**
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*
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* @brief Get the d-cache line size.
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*
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* The API is provided to get the d-cache line size.
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*
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* @return size of the d-cache line or 0 if the d-cache is not enabled.
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*/
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static inline size_t sys_cache_data_line_size_get(void)
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{
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#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
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return cache_data_line_size_get();
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#elif (CONFIG_DCACHE_LINE_SIZE != 0)
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return CONFIG_DCACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(CPU, d_cache_line_size, 0);
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#endif
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}
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/*
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*
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* @brief Get the i-cache line size.
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*
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* The API is provided to get the i-cache line size.
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*
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* @return size of the i-cache line or 0 if the i-cache is not enabled.
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*/
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static inline size_t sys_cache_instr_line_size_get(void)
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{
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#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
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return cache_instr_line_size_get();
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#elif (CONFIG_ICACHE_LINE_SIZE != 0)
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return CONFIG_ICACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(CPU, i_cache_line_size, 0);
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#endif
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}
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#include <syscalls/cache.h>
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
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