374 lines
8.9 KiB
C
374 lines
8.9 KiB
C
/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_gpio
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#include <drivers/gpio.h>
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#include <drivers/interrupt_controller/gd32_exti.h>
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#include <soc.h>
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#include "gpio_utils.h"
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#ifdef CONFIG_GD32_HAS_AF_PINMUX
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/** SYSCFG DT node */
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#define SYSCFG_NODE DT_NODELABEL(syscfg)
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#else
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/** AFIO DT node */
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#define AFIO_NODE DT_NODELABEL(afio)
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/** GPIO mode: analog (CTL bits) */
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#define CTL_MODE_ANALOG 0x0U
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/** GPIO mode: input floating (CTL bits) */
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#define CTL_MODE_INP_FLOAT 0x4U
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/** GPIO mode: input with pull-up/down (CTL bits) */
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#define CTL_MODE_INP_PUPD 0x8U
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/** GPIO mode: output push-pull @ 2MHz (CTL bits) */
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#define CTL_MODE_OUT_PP 0x2U
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/** GPIO mode: output open-drain @ 2MHz (CTL bits) */
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#define CTL_MODE_OUT_OD 0x6U
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#endif /* CONFIG_GD32_HAS_AF_PINMUX */
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/** EXTISS mask */
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#define EXTISS_MSK 0xFU
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/** EXTISS line step size */
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#define EXTISS_STEP 4U
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/** EXTISS line shift */
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#define EXTISS_LINE_SHIFT(pin) (EXTISS_STEP * ((pin) % EXTISS_STEP))
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struct gpio_gd32_config {
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struct gpio_driver_config common;
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uint32_t reg;
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uint32_t rcu_periph_clock;
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};
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struct gpio_gd32_data {
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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};
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/**
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* @brief EXTI ISR callback.
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*
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* @param line EXTI line (equals to GPIO pin number).
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* @param arg GPIO port instance.
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*/
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static void gpio_gd32_isr(uint8_t line, void *arg)
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{
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const struct device *dev = arg;
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struct gpio_gd32_data *data = dev->data;
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gpio_fire_callbacks(&data->callbacks, dev, BIT(line));
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}
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/**
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* @brief Configure EXTI source selection register.
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*
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* @param port GPIO port instance.
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* @param pin GPIO pin number.
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*
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* @retval 0 on success.
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* @retval -EINVAL if pin is not valid.
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*/
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static int gpio_gd32_configure_extiss(const struct device *port,
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gpio_pin_t pin)
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{
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const struct gpio_gd32_config *config = port->config;
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uint8_t port_index, shift;
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volatile uint32_t *extiss;
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switch (pin / EXTISS_STEP) {
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#ifdef CONFIG_GD32_HAS_AF_PINMUX
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case 0U:
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extiss = &SYSCFG_EXTISS0;
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break;
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case 1U:
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extiss = &SYSCFG_EXTISS1;
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break;
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case 2U:
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extiss = &SYSCFG_EXTISS2;
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break;
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case 3U:
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extiss = &SYSCFG_EXTISS3;
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break;
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#else
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case 0U:
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extiss = &AFIO_EXTISS0;
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break;
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case 1U:
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extiss = &AFIO_EXTISS1;
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break;
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case 2U:
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extiss = &AFIO_EXTISS2;
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break;
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case 3U:
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extiss = &AFIO_EXTISS3;
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break;
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#endif /* CONFIG_GD32_HAS_AF_PINMUX */
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default:
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return -EINVAL;
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}
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port_index = (config->reg - GPIOA) / (GPIOB - GPIOA);
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shift = EXTISS_LINE_SHIFT(pin);
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*extiss &= ~(EXTISS_MSK << shift);
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*extiss |= port_index << shift;
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return 0;
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}
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static inline int gpio_gd32_configure(const struct device *port, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_gd32_config *config = port->config;
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#ifdef CONFIG_GD32_HAS_AF_PINMUX
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uint32_t ctl, pupd;
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ctl = GPIO_CTL(config->reg);
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ctl &= ~GPIO_MODE_MASK(pin);
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pupd = GPIO_PUD(config->reg);
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pupd &= ~GPIO_PUPD_MASK(pin);
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if ((flags & GPIO_OUTPUT) != 0U) {
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ctl |= GPIO_MODE_SET(pin, GPIO_MODE_OUTPUT);
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if ((flags & GPIO_SINGLE_ENDED) != 0U) {
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if ((flags & GPIO_LINE_OPEN_DRAIN) != 0U) {
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GPIO_OMODE(config->reg) |= BIT(pin);
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} else {
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return -ENOTSUP;
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}
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} else {
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GPIO_OMODE(config->reg) &= ~BIT(pin);
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}
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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GPIO_BOP(config->reg) = BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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GPIO_BC(config->reg) = BIT(pin);
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}
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} else if ((flags & GPIO_INPUT) != 0U) {
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ctl |= GPIO_MODE_SET(pin, GPIO_MODE_INPUT);
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} else {
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ctl |= GPIO_MODE_SET(pin, GPIO_MODE_ANALOG);
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}
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if ((flags & GPIO_PULL_UP) != 0U) {
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pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_PULLUP);
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} else if ((flags & GPIO_PULL_DOWN) != 0U) {
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pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_PULLDOWN);
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} else {
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pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_NONE);
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}
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GPIO_PUD(config->reg) = pupd;
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GPIO_CTL(config->reg) = ctl;
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#else
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volatile uint32_t *ctl_reg;
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uint32_t ctl, pin_bit;
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pin_bit = BIT(pin);
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if (pin < 8U) {
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ctl_reg = &GPIO_CTL0(config->reg);
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} else {
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ctl_reg = &GPIO_CTL1(config->reg);
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pin -= 8U;
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}
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ctl = *ctl_reg;
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ctl &= ~GPIO_MODE_MASK(pin);
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if ((flags & GPIO_OUTPUT) != 0U) {
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if ((flags & GPIO_SINGLE_ENDED) != 0U) {
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if ((flags & GPIO_LINE_OPEN_DRAIN) != 0U) {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_OUT_OD);
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} else {
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return -ENOTSUP;
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}
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} else {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_OUT_PP);
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}
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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GPIO_BOP(config->reg) = pin_bit;
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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GPIO_BC(config->reg) = pin_bit;
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}
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} else if ((flags & GPIO_INPUT) != 0U) {
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if ((flags & GPIO_PULL_UP) != 0U) {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_PUPD);
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GPIO_BOP(config->reg) = pin_bit;
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} else if ((flags & GPIO_PULL_DOWN) != 0U) {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_PUPD);
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GPIO_BC(config->reg) = pin_bit;
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} else {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_FLOAT);
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}
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} else {
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ctl |= GPIO_MODE_SET(pin, CTL_MODE_ANALOG);
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}
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*ctl_reg = ctl;
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#endif /* CONFIG_GD32_HAS_AF_PINMUX */
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return 0;
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}
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static int gpio_gd32_port_get_raw(const struct device *port, uint32_t *value)
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{
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const struct gpio_gd32_config *config = port->config;
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*value = GPIO_ISTAT(config->reg);
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return 0;
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}
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static int gpio_gd32_port_set_masked_raw(const struct device *port,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_gd32_config *config = port->config;
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GPIO_OCTL(config->reg) =
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(GPIO_OCTL(config->reg) & ~mask) | (value & mask);
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return 0;
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}
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static int gpio_gd32_port_set_bits_raw(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_gd32_config *config = port->config;
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GPIO_BOP(config->reg) = pins;
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return 0;
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}
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static int gpio_gd32_port_clear_bits_raw(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_gd32_config *config = port->config;
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GPIO_BC(config->reg) = pins;
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return 0;
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}
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static int gpio_gd32_port_toggle_bits(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_gd32_config *config = port->config;
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#ifdef CONFIG_GD32_HAS_AF_PINMUX
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GPIO_TG(config->reg) = pins;
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#else
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GPIO_OCTL(config->reg) ^= pins;
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#endif /* CONFIG_GD32_HAS_AF_PINMUX */
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return 0;
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}
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static int gpio_gd32_pin_interrupt_configure(const struct device *port,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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if (mode == GPIO_INT_MODE_DISABLED) {
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gd32_exti_disable(pin);
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(void)gd32_exti_configure(pin, NULL, NULL);
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gd32_exti_trigger(pin, GD32_EXTI_TRIG_NONE);
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} else if (mode == GPIO_INT_MODE_EDGE) {
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int ret;
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ret = gd32_exti_configure(pin, gpio_gd32_isr, (void *)port);
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if (ret < 0) {
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return ret;
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}
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ret = gpio_gd32_configure_extiss(port, pin);
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if (ret < 0) {
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return ret;
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}
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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gd32_exti_trigger(pin, GD32_EXTI_TRIG_FALLING);
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break;
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case GPIO_INT_TRIG_HIGH:
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gd32_exti_trigger(pin, GD32_EXTI_TRIG_RISING);
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break;
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case GPIO_INT_TRIG_BOTH:
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gd32_exti_trigger(pin, GD32_EXTI_TRIG_BOTH);
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break;
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default:
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return -ENOTSUP;
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}
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gd32_exti_enable(pin);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_gd32_manage_callback(const struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_gd32_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static const struct gpio_driver_api gpio_gd32_api = {
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.pin_configure = gpio_gd32_configure,
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.port_get_raw = gpio_gd32_port_get_raw,
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.port_set_masked_raw = gpio_gd32_port_set_masked_raw,
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.port_set_bits_raw = gpio_gd32_port_set_bits_raw,
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.port_clear_bits_raw = gpio_gd32_port_clear_bits_raw,
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.port_toggle_bits = gpio_gd32_port_toggle_bits,
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.pin_interrupt_configure = gpio_gd32_pin_interrupt_configure,
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.manage_callback = gpio_gd32_manage_callback,
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};
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static int gpio_gd32_init(const struct device *port)
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{
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const struct gpio_gd32_config *config = port->config;
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rcu_periph_clock_enable(config->rcu_periph_clock);
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#ifdef CONFIG_GD32_HAS_AF_PINMUX
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/* enable access to SYSCFG_EXTISSn registers */
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rcu_periph_clock_enable(DT_PROP(SYSCFG_NODE, rcu_periph_clock));
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#else
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/* enable access to AFIO_EXTISSn registers */
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rcu_periph_clock_enable(DT_PROP(AFIO_NODE, rcu_periph_clock));
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#endif /* CONFIG_GD32_HAS_AF_PINMUX */
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return 0;
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}
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#define GPIO_GD32_DEFINE(n) \
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static const struct gpio_gd32_config gpio_gd32_config##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.reg = DT_INST_REG_ADDR(n), \
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.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \
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}; \
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\
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static struct gpio_gd32_data gpio_gd32_data##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &gpio_gd32_init, NULL, &gpio_gd32_data##n, \
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&gpio_gd32_config##n, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_gd32_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_GD32_DEFINE)
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