zephyr/arch/riscv/Kconfig

# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
# SPDX-License-Identifier: Apache-2.0

menu "RISCV Options"
	depends on RISCV

config ARCH
	string
	default "riscv64" if 64BIT
	default "riscv32"

config COMPRESSED_ISA
	bool
	default y if 64BIT

config RISCV_ATOMICS_ISA
	bool "RISC-V atomics 'a' extension"
	default y

config RISCV_MUL_ISA
	bool "RISC-V HW multiply 'm' extension"
	default y

config FLOAT_HARD
	bool "Hard-float calling convention"
	default y
	depends on FPU
	help
	  This option enables the hard-float calling convention.

config RISCV_GP
	bool "RISC-V global pointer relative addressing"
	default n
	help
	  Use global pointer relative addressing for small globals declared
	  anywhere in the executable. It can benefit performance and reduce
	  the code size.

	  Note: To support this feature, RISC-V SoC needs to initialize
	  global pointer at program start or earlier than any instruction
	  using GP relative addressing.

menu "RISCV Processor Options"

config CORE_E31
	bool "Use E31 core"
	select RISCV_PMP
	select ARCH_HAS_USERSPACE
	select ARCH_HAS_STACK_PROTECTION if PMP_STACK_GUARD
	default n
	help
	  This option signifies the use of a core of the E31 family.

config INCLUDE_RESET_VECTOR
	bool "Include Reset vector"
	help
	  Include the reset vector stub, which initializes the stack and
	  prepares for running C code.

config RISCV_SOC_CONTEXT_SAVE
	bool "SOC-based context saving in IRQ handlers"
	select RISCV_SOC_OFFSETS
	help
	  Enable low-level SOC-specific context management, for SOCs
	  with extra state that must be saved when entering an
	  interrupt/exception, and restored on exit. If unsure, leave
	  this at the default value.

	  Enabling this option requires that the SoC provide a
	  soc_context.h header which defines the following macros:

	  - SOC_ESF_MEMBERS: structure component declarations to
	    allocate space for. The last such declaration should not
	    end in a semicolon, for portability. The generic RISC-V
	    architecture code will allocate space for these members in
	    a "struct soc_esf" type (typedefed to soc_esf_t), which will
	    be available if arch.h is included.

	  - SOC_ESF_INIT: structure contents initializer for struct soc_esf
	    state. The last initialized member should not end in a comma.

	  The generic architecture IRQ wrapper will also call
	  \_\_soc_save_context and \_\_soc_restore_context routines at
	  ISR entry and exit, respectively. These should typically
	  be implemented in assembly. If they were C functions, they
	  would have these signatures:

	  ``void __soc_save_context(soc_esf_t *state);``

	  ``void __soc_restore_context(soc_esf_t *state);``

	  The calls obey standard calling conventions; i.e., the state
	  pointer address is in a0, and ra contains the return address.

config RISCV_SOC_OFFSETS
	bool "SOC-based offsets"
	help
	  Enabling this option requires that the SoC provide a soc_offsets.h
	  header which defines the following macros:

	  - GEN_SOC_OFFSET_SYMS(): a macro which expands to
	    GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
	    to ensure offset macros for SOC_ESF_MEMBERS are defined
	    in offsets.h. The last one should not end in a semicolon.
	    See gen_offset.h for more details.

config RISCV_SOC_INTERRUPT_INIT
	bool "SOC-based interrupt initialization"
	help
	  Enable SOC-based interrupt initialization
	  (call soc_interrupt_init, within _IntLibInit when enabled)

config RISCV_SOC_MCAUSE_EXCEPTION_MASK
	hex
	default 0x7FFFFFFFFFFFFFFF if 64BIT
	default 0x7FFFFFFF
	help
	  Specify the bits to use for exception code in mcause register.

config RISCV_GENERIC_TOOLCHAIN
	bool "Compile using generic riscv32 toolchain"
	default y
	help
	  Compile using generic riscv32 toolchain.
	  Allow SOCs that have custom extended riscv ISA to still
	  compile with generic riscv32 toolchain.

config RISCV_HAS_CPU_IDLE
	bool "Does SOC has CPU IDLE instruction"
	help
	  Does SOC has CPU IDLE instruction

config GEN_ISR_TABLES
	default y

config GEN_IRQ_VECTOR_TABLE
	default n

config NUM_IRQS
	int

menuconfig RISCV_PMP
	bool "RISC-V PMP Support"
	default n
	select THREAD_STACK_INFO
	select CPU_HAS_MPU
	select MPU
	select SRAM_REGION_PERMISSIONS
	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
	select PMP_POWER_OF_TWO_ALIGNMENT if USERSPACE
	help
	  MCU implements Physical Memory Protection.

if RISCV_PMP
source "arch/riscv/core/pmp/Kconfig"
endif #RISCV_PMP

endmenu

config MAIN_STACK_SIZE
	default 4096 if 64BIT

config TEST_EXTRA_STACK_SIZE
	default 1024

config CMSIS_THREAD_MAX_STACK_SIZE
	default 1024 if 64BIT

config CMSIS_V2_THREAD_MAX_STACK_SIZE
	default 1024 if 64BIT

endmenu