60 lines
1.9 KiB
Plaintext
60 lines
1.9 KiB
Plaintext
# ARM architecture configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "ARM Options"
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depends on ARM
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config ARCH
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default "arm"
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config CPU_CORTEX
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bool
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help
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This option signifies the use of a CPU of the Cortex family.
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config ARM_CUSTOM_INTERRUPT_CONTROLLER
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bool
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depends on !CPU_CORTEX_M
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help
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This option indicates that the ARM CPU is connected to a custom (i.e.
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non-GIC) interrupt controller.
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A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
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allow interfacing to a custom external interrupt controller and this
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option must be selected when such cores are connected to an interrupt
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controller that is not the ARM Generic Interrupt Controller (GIC).
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When this option is selected, the architecture interrupt control
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functions are mapped to the SoC interrupt control interface, which is
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implemented at the SoC level.
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N.B. This option is only applicable to the Cortex-A and Cortex-R
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family cores. The Cortex-M family cores are always equipped with
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the ARM Nested Vectored Interrupt Controller (NVIC).
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config CODE_DATA_RELOCATION
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bool "Relocate code/data sections"
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depends on CPU_CORTEX_M
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help
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When selected this will relocate .text, data and .bss sections from
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the specified files and places it in the required memory region. The
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files should be specified in the CMakeList.txt file with
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a cmake API zephyr_code_relocate().
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config CODE_DATA_RELOCATION_SRAM
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bool "Relocate code/data sections to SRAM"
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depends on CPU_CORTEX_M
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select CODE_DATA_RELOCATION
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help
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When selected this will relocate .text, data and .bss sections from
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the specified files and places it in SRAM. The files should be specified
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in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This
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config is used to create an MPU entry for the SRAM space used for code
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relocation.
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rsource "core/aarch32/Kconfig"
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endmenu
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