144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <misc/util.h>
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#include <system_timer.h>
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#include <soc.h>
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/*
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* This is just a getting started point.
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*
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* Assumptions and limitations:
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*
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* - system clock based on an LPTMR instance, clocked by SIRC output
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* SIRCDIV3, prescaler divide-by-1, SIRC at 8MHz
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* - no tickless
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*/
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#define CYCLES_PER_SEC CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/*
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* As a simplifying assumption, we only support a clock ticking at the
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* SIRC reset rate of 8MHz.
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*/
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#if MHZ(8) != CYCLES_PER_SEC
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#error "system timer misconfiguration; unsupported clock rate"
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#endif
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#define SYSTEM_TIMER_INSTANCE \
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((LPTMR_Type *)(DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_BASE_ADDRESS))
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#define SYSTEM_TIMER_IRQ_PRIO 0
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#define SIRC_RANGE_8MHZ SCG_SIRCCFG_RANGE(1)
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#define SIRCDIV3_DIVIDE_BY_1 1
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#define PCS_SOURCE_SIRCDIV3 0
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struct device; /* forward declaration; type is not used. */
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static volatile u32_t cycle_count;
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static void lptmr_irq_handler(struct device *unused)
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{
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ARG_UNUSED(unused);
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SYSTEM_TIMER_INSTANCE->CSR |= LPTMR_CSR_TCF(1); /* Rearm timer. */
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cycle_count += CYCLES_PER_TICK; /* Track cycles. */
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z_clock_announce(1); /* Poke the scheduler. */
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}
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int z_clock_driver_init(struct device *unused)
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{
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u32_t csr, psr, sircdiv; /* LPTMR registers */
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ARG_UNUSED(unused);
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IRQ_CONNECT(DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ,
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SYSTEM_TIMER_IRQ_PRIO, lptmr_irq_handler, NULL, 0);
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if ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCEN_MASK) == SCG_SIRCCSR_SIRCEN(0)) {
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/*
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* SIRC is on by default, so something else turned it off.
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*
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* This is incompatible with this driver, which is SIRC-based.
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*/
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return -ENODEV;
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}
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/* Disable the timer and clear any pending IRQ. */
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csr = SYSTEM_TIMER_INSTANCE->CSR;
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csr &= ~LPTMR_CSR_TEN(0);
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csr |= LPTMR_CSR_TFC(1);
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SYSTEM_TIMER_INSTANCE->CSR = csr;
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/*
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* Set up the timer clock source and configure the timer.
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*/
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/*
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* SIRCDIV3 is the SIRC divider for LPTMR (SoC dependent).
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* Pass it directly through without any divider.
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*/
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sircdiv = SCG->SIRCDIV;
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sircdiv &= ~SCG_SIRCDIV_SIRCDIV3_MASK;
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sircdiv |= SCG_SIRCDIV_SIRCDIV3(SIRCDIV3_DIVIDE_BY_1);
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SCG->SIRCDIV = sircdiv;
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/*
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* TMS = 0: time counter mode, not pulse counter
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* TCF = 0: reset counter register on reaching compare value
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* TDRE = 0: disable DMA request
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*/
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csr &= ~(LPTMR_CSR_TMS(1) | LPTMR_CSR_TFC(1) | LPTMR_CSR_TDRE(1));
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/*
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* TIE = 1: enable interrupt
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*/
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csr |= LPTMR_CSR_TIE(1);
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SYSTEM_TIMER_INSTANCE->CSR = csr;
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/*
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* PCS = 0: clock source is SIRCDIV3 (SoC dependent)
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* PBYP = 1: bypass the prescaler
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*/
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psr = SYSTEM_TIMER_INSTANCE->PSR;
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psr &= ~LPTMR_PSR_PCS_MASK;
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psr |= (LPTMR_PSR_PBYP(1) | LPTMR_PSR_PCS(PCS_SOURCE_SIRCDIV3));
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SYSTEM_TIMER_INSTANCE->PSR = psr;
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/*
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* Set compare register to the proper tick count. The check
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* here makes sure SIRC is left at its default reset value to
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* make the defconfig setting work properly.
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*
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* TODO: be smarter to meet arbitrary Kconfig settings.
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*/
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if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) != SIRC_RANGE_8MHZ) {
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return -EINVAL;
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}
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SYSTEM_TIMER_INSTANCE->CMR = CYCLES_PER_TICK;
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/*
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* Enable interrupts and the timer. There's no need to clear the
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* TFC bit in the csr variable, as it's already clear.
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*/
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irq_enable(DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ);
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csr = SYSTEM_TIMER_INSTANCE->CSR;
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csr |= LPTMR_CSR_TEN(1);
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SYSTEM_TIMER_INSTANCE->CSR = csr;
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return 0;
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}
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u32_t z_timer_cycle_get_32(void)
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{
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return cycle_count + SYSTEM_TIMER_INSTANCE->CNR;
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}
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/*
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* Since we're not tickless, this is identically zero.
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*/
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u32_t z_clock_elapsed(void)
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{
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return 0;
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}
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