zephyr/soc/xtensa/sample_controller
Lauren Murphy c1711997bc debug: coredump: add xtensa coredump
Adds Xtensa as supported architecture for coredump. Fixes
a few typos in documentation, Kconfig and a C file. Dumps
minimal set of registers shown by 'info registers' in GDB
for the sample_controller and ESP32 SOCs. Updates tests.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2021-12-14 07:40:55 -05:00
..
include
CMakeLists.txt
Kconfig.defconfig xtensa: set toolchain variant per SoC 2020-12-20 14:30:50 -05:00
Kconfig.soc debug: coredump: add xtensa coredump 2021-12-14 07:40:55 -05:00
linker.ld linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00