313 lines
8.7 KiB
Plaintext
313 lines
8.7 KiB
Plaintext
# Kconfig - x86 general configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "x86 SoC Selection"
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depends on X86
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source "arch/x86/soc/*/Kconfig.soc"
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endchoice
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menu "X86 Architecture Options"
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depends on X86
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# Include these first so that any properties (e.g. defaults) below can be
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# overriden (by defining symbols in multiple locations)
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source "arch/x86/soc/*/Kconfig"
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config ARCH
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default "x86"
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config ARCH_DEFCONFIG
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string
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default "arch/x86/defconfig"
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source "arch/x86/core/Kconfig"
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#
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# Hidden CPU family configs which are to be selected by
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# individual SoC.
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#
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config CPU_ATOM
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# Hidden
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bool
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select CMOV
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Atom family.
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config CPU_MINUTEIA
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# Hidden
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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bool
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help
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This option signifies the use of a CPU from the Minute IA family.
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config CPU_APOLLO_LAKE
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# Hidden
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bool
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select CMOV
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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menu "Processor Capabilities"
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config X86_IAMCU
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bool "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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menu "Memory Management"
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config X86_MMU
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bool "Enable Memory Management Unit"
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help
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This options enables the memory management unit present in x86. Enabling
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this will create boot time page table structure.
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config X86_PAE_MODE
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bool "Enable PAE page tables"
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depends on X86_MMU
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help
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When selected the Page address extension mode is enabled. The PAE
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page tables provides a mechanism to selectively disable execution.
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So any Page Table Entry (PTE) that sets the XD bit will have all
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instruction fetches disabled in that 4KB region. The amount of RAM
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needed for PAE tables is more than twice that of 32-Bit paging
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because each PAE entry is 64bits wide.
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Note: Do not enable in RAM constrained devices.
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config X86_NO_MELTDOWN
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Meltdown CPU vulnerability.
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config X86_NO_SPECTRE_V2
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bool
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default y
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V2 CPU vulnerability.
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config X86_NO_SPECTRE_V4
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bool
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default y
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V4 CPU vulnerability.
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endmenu
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config X86_ENABLE_TSS
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bool
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help
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This hidden option enables defining a Task State Segment (TSS) for
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kernel execution. This is needed to handle double-faults or
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do privilege elevation. It also defines a special TSS and handler
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for correctly handling double-fault exceptions, instead of just
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letting the system triple-fault and reset.
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config X86_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option leverages the MMU to cause a system fatal error if the
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bounds of the current process stack are overflowed. This is done
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by preceding all stack areas with a 4K guard page.
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config X86_USERSPACE
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bool
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default y if USERSPACE
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select THREAD_STACK_INFO
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option enables APIs to drop a thread's privileges down to ring 3,
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supporting user-level threads that are protected from each other and
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from crashing the kernel.
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menu "Architecture Floating Point Options"
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depends on CPU_HAS_FPU
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config SSE
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bool "SSE registers"
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depends on FLOAT
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help
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This option enables the use of SSE registers by threads.
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config SSE_FP_MATH
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bool "Compiler-generated SSEx instructions"
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depends on SSE
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when preemptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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endmenu
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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config ISA_IA32
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bool
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default y
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help
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This option signifies the use of a CPU based on the Intel IA-32
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instruction set architecture.
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config IA32_LEGACY_IO_PORTS
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bool "Support IA32 legacy IO ports"
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depends on ISA_IA32
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help
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This option enables IA32 legacy IO ports. Note these are much slower
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than memory access, so they should be used in last resort.
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config CMOV
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bool
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help
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This option signifies the use of an Intel CPU that supports
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the CMOV instruction.
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config CACHE_LINE_SIZE_DETECT
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bool "Detect cache line size at runtime"
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default y
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help
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This option enables querying the CPUID register for finding the cache line
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size at the expense of taking more memory and code and a slightly increased
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boot time.
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If the CPU's cache line size is known in advance, disable this option and
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manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 64 if CPU_ATOM
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default 0
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help
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Size in bytes of a CPU cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_FLUSHING
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool "Detect support of CLFLUSH instruction at runtime"
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depends on CACHE_FLUSHING
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default y
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depends on CLFLUSH_DETECT
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config CACHE_FLUSHING
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bool "Enable cache flushing mechanism"
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help
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This links in the sys_cache_flush() function. A mechanism for flushing the
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cache must be selected as well. By default, that mechanism is discovered at
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runtime.
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config PIC_DISABLE
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bool "Disable PIC"
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help
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This option disables all interrupts on the PIC
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config X86_KERNEL_OOPS
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bool "Enable handling of kernel oops as an exception"
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default y
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help
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Enable handling of k_oops() API as a CPU exception, which will provide
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extra debugging information such as program counter and register
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values when the oops is triggered. Requires an entry in the IDT.
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config X86_KERNEL_OOPS_VECTOR
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int "IDT vector to use for kernel oops"
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default 62 if MVIC
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default 33 if !MVIC
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range 32 255
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depends on X86_KERNEL_OOPS
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help
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Specify the IDT vector to use for the kernel oops exception handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 63 if MVIC
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default 32 if !MVIC
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range 32 255
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depends on IRQ_OFFLOAD
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help
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Specify the IDT vector to use for the IRQ offload interrupt handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config XIP
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default n
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config X86_FIXED_IRQ_MAPPING
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bool
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help
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Specify whether the current interrupt controller in use has a fixed
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mapping between IDT vectors and IRQ lines.
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endmenu
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endmenu
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