32 lines
510 B
Plaintext
32 lines
510 B
Plaintext
/*
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* Copyright (c) 2019 Intel Corp.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "qemu_x86.dts"
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/ {
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cpus {
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,x86";
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d-cache-line-size = <64>;
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reg = <1>;
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};
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};
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};
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&pcie0 {
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smbus0: smbus0 {
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compatible = "intel,pch-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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vendor-id = <0x8086>;
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device-id = <0x2930>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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};
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