139 lines
3.2 KiB
Plaintext
139 lines
3.2 KiB
Plaintext
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/nxp/nxp_s32z27x_r52.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@0;
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/delete-node/ cpu@1;
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/delete-node/ cpu@2;
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/delete-node/ cpu@3;
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};
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soc {
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stm0: stm@76a00000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76a00000 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
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status = "disabled";
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};
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stm1: stm@76a10000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76a10000 0x10000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
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status = "disabled";
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};
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stm2: stm@76820000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76820000 0x10000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
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status = "disabled";
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};
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stm3: stm@76830000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76830000 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
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status = "disabled";
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};
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swt0: watchdog@76800000 {
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compatible = "nxp,s32-swt";
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reg = <0x76800000 0x10000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt1: watchdog@76810000 {
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compatible = "nxp,s32-swt";
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reg = <0x76810000 0x10000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt2: watchdog@76a20000 {
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compatible = "nxp,s32-swt";
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reg = <0x76a20000 0x10000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt3: watchdog@76a30000 {
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compatible = "nxp,s32-swt";
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reg = <0x76a30000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt4: watchdog@76940000 {
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compatible = "nxp,s32-swt";
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reg = <0x76940000 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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pit0: pit@76950000 {
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compatible = "nxp,pit";
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reg = <0x76950000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_P1_REG_INTF_CLK>;
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max-load-value = <0x00ffffff>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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pit0_channel0: pit0_channel@0 {
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compatible = "nxp,pit-channel";
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reg = <0>;
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status = "disabled";
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};
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pit0_channel1: pit0_channel@1 {
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compatible = "nxp,pit-channel";
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reg = <1>;
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status = "disabled";
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};
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pit0_channel2: pit0_channel@2 {
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compatible = "nxp,pit-channel";
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reg = <2>;
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status = "disabled";
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};
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pit0_channel3: pit0_channel@3 {
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compatible = "nxp,pit-channel";
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reg = <3>;
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status = "disabled";
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};
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pit0_channel4: pit0_channel@4 {
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compatible = "nxp,pit-channel";
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reg = <4>;
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status = "disabled";
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};
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pit0_channel5: pit0_channel@5 {
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compatible = "nxp,pit-channel";
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reg = <5>;
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status = "disabled";
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};
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};
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};
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};
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