173 lines
3.2 KiB
ArmAsm
173 lines
3.2 KiB
ArmAsm
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include "boot.h"
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#include "macro_priv.inc"
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_ASM_FILE_PROLOGUE
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/*
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* Platform specific pre-C init code
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*
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* Note: - Stack is not yet available
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* - x23, x24 and x25 must be preserved
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*/
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WTEXT(z_arm64_el3_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el3_plat_prep_c)
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ret
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WTEXT(z_arm64_el2_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el2_plat_prep_c)
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ret
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WTEXT(z_arm64_el1_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el1_plat_prep_c)
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ret
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/*
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* Set the minimum necessary to safely call C code
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*/
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GTEXT(__reset_prep_c)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
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/* return address: x23 */
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mov x23, x30
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switch_el x0, 3f, 2f, 1f
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3:
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/* Reinitialize SCTLR from scratch in EL3 */
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ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
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msr sctlr_el3, x0
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/* Custom plat prep_c init */
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bl z_arm64_el3_plat_prep_c
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/* Set SP_EL1 */
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msr sp_el1, x24
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b out
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2:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el2
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el2, x0
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/* Custom plat prep_c init */
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bl z_arm64_el2_plat_prep_c
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/* Set SP_EL1 */
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msr sp_el1, x24
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b out
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1:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el1
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el1, x0
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/* Custom plat prep_c init */
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bl z_arm64_el1_plat_prep_c
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/* Set SP_EL1. We cannot use sp_el1 at EL1 */
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msr SPSel, #1
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mov sp, x24
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out:
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isb
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/* Select SP_EL0 */
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msr SPSel, #0
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/* Initialize stack */
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mov sp, x24
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ret x23
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/*
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* Reset vector
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*
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* Ran when the system comes out of reset. The processor is in thread mode with
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* privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
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* area in SRAM.
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*/
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GTEXT(__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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GTEXT(__start)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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/* Mask all exceptions */
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msr DAIFSet, #0xf
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#if CONFIG_MP_NUM_CPUS > 1
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ldr x0, =arm64_cpu_boot_params
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get_cpu_id x1
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ldr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
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cmp x2, #-1
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beq primary_core
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/* loop until our turn comes */
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1: dmb ld
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ldr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
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cmp x1, x2
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bne 1b
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/* we can now load our stack pointer value and move on */
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ldr x24, [x0, #BOOT_PARAM_SP_OFFSET]
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ldr x25, =z_arm64_secondary_prep_c
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b 2f
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primary_core:
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/* advertise ourself */
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str x1, [x0, #BOOT_PARAM_MPID_OFFSET]
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#endif
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/* load primary stack and entry point */
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ldr x24, =(z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)
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ldr x25, =z_arm64_prep_c
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2:
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/* Prepare for calling C code */
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bl __reset_prep_c
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/* Platform hook for highest EL */
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bl z_arm64_el_highest_init
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switch_el:
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switch_el x0, 3f, 2f, 1f
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3:
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/* EL3 init */
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bl z_arm64_el3_init
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/* Get next EL */
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adr x0, switch_el
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bl z_arm64_el3_get_next_el
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eret
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2:
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/* EL2 init */
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bl z_arm64_el2_init
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/* Move to EL1 with all exceptions masked */
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mov_imm x0, (SPSR_DAIF_MASK | SPSR_MODE_EL1T)
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msr spsr_el2, x0
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adr x0, 1f
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msr elr_el2, x0
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eret
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1:
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/* EL1 init */
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bl z_arm64_el1_init
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/* Enable SError interrupts */
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msr DAIFClr, #(DAIFCLR_ABT_BIT)
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isb
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ret x25 /* either z_arm64_prep_c or z_arm64_secondary_prep_c */
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