138 lines
3.3 KiB
Plaintext
138 lines
3.3 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#define INT_UARTA0 21 // UART0 Rx and Tx
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#define INT_UARTA1 22 // UART1 Rx and Tx
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#define INT_I2CA0 24 // I2C controller
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#define INT_ADCCH0 30 // ADC channel 0
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#define INT_ADCCH1 31 // ADC channel 1
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#define INT_ADCCH2 32 // ADC channel 2
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#define INT_ADCCH3 33 // ADC channel 3
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#define INT_WDT 34 // Watchdog Timer
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/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
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/* which are offset by 16: */
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#define EXP_UARTA0 (INT_UARTA0 - 16)
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#define EXP_UARTA1 (INT_UARTA1 - 16)
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#define EXP_I2CA0 (INT_I2CA0 - 16)
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#define EXP_ADCCH0 (INT_ADCCH0 - 16)
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#define EXP_ADCCH1 (INT_ADCCH1 - 16)
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#define EXP_ADCCH2 (INT_ADCCH2 - 16)
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#define EXP_ADCCH3 (INT_ADCCH3 - 16)
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#define EXP_WDT (INT_WDT - 16)
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#define EXC_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */
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#define EXC_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */
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#define EXC_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */
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#define EXC_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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flash0: serial-flash@0 {
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compatible = "serial-flash";
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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#clock-cells = <0>;
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};
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soc {
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uart0: uart@4000c000 {
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compatible = "ti,cc32xx-uart";
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reg = <0x4000c000 0x4c>;
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interrupts = <EXP_UARTA0 3>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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uart1: uart@4000d000 {
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compatible = "ti,cc32xx-uart";
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reg = <0x4000d000 0x4c>;
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interrupts = <EXP_UARTA1 3>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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i2c0: i2c@40020000 {
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compatible = "ti,cc32xx-i2c";
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clocks = <&sysclk>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40020000 0xfc8>;
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interrupts = <EXP_I2CA0 3>;
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status = "disabled";
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};
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gpioa0: gpio@40004000 {
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compatible = "ti,cc32xx-gpio";
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reg = <0x40004000 0x1000>;
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interrupts = <0 1>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioa1: gpio@40005000 {
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compatible = "ti,cc32xx-gpio";
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reg = <0x40005000 0x1000>;
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interrupts = <1 1>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioa2: gpio@40006000 {
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compatible = "ti,cc32xx-gpio";
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reg = <0x40006000 0x1000>;
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interrupts = <2 1>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioa3: gpio@40007000 {
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compatible = "ti,cc32xx-gpio";
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reg = <0x40007000 0x1000>;
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interrupts = <3 1>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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adc0: adc@4402e800 {
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compatible = "ti,cc32xx-adc";
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reg = <0x4402E800 0x100>;
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interrupts = <EXP_ADCCH0 3>, <EXP_ADCCH1 3>, <EXP_ADCCH2 3>, <EXP_ADCCH3 3>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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wdt0: watchdog@40000000 {
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compatible = "ti,cc32xx-watchdog";
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reg = <0x40000000 0x1000>;
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interrupts = <EXP_WDT 0>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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