Nicolas Pitre a211970b42 riscv: improve contended FPU switching ... We can leverage the FPU dirty state as an indicator for preemptively reloading the FPU content when a thread that did use the FPU before being scheduled out is scheduled back in. This avoids the FPU access trap overhead when switching between multiple threads with heavy FPU usage. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2023-01-24 15:26:18 +01:00
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arc	treewide: Use CONFIG_CPP instead of CONFIG_CPLUSPLUS	2023-01-13 17:42:55 -05:00
arm	arch: arm: aarch32: cortex_a_r: disable interrupts before context switching	2023-01-18 16:22:29 +01:00
arm64	arch/arm64: Implement ASID support in ARM64 MMU	2022-12-13 17:21:11 +09:00
common	include: add missing irq.h include	2022-10-11 18:05:17 +02:00
mips	include: types: remove ulong_t	2022-09-06 18:16:33 +02:00
nios2	arch: comply to coding guidelines MISRA C:2012 Rule 14.4	2022-07-20 09:28:38 -05:00
posix	arch: posix: Declare _posix_zephyr_main with int return type	2022-11-05 16:41:45 +09:00
riscv	riscv: improve contended FPU switching	2023-01-24 15:26:18 +01:00
sparc	SPARC: reduce z_thread_entry_wrapper	2022-08-03 12:05:49 +02:00
x86	arch/x86: Fix compilation error	2023-01-10 14:06:33 +00:00
xtensa	xtensa: stop execution under simulator for double exception	2023-01-23 10:09:18 +00:00
CMakeLists.txt	…
Kconfig	userspace: Do not use --relax flag	2023-01-16 11:20:32 +00:00