63 lines
1.5 KiB
YAML
63 lines
1.5 KiB
YAML
# Copyright (c) 2020, Linaro limited
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 QSPI device representation. A stm32 quadspi node would typically
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looks to this:
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&quadspi {
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pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
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&quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
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&quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
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dmas = <&dma1 5 5 0x0000 0x03>;
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dma-names = "tx_rx";
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status = "okay";
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};
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compatible: "st,stm32-qspi"
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include: [base.yaml, pinctrl-device.yaml]
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bus: qspi
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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dmas:
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description: |
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Optional DMA channel specifier. If DMA should be used, specifier should
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hold a phandle reference to the dma controller, the channel number,
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the slot number, channel configuration and finally features.
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For example dmas for TX/RX on QSPI
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dmas = <&dma1 5 5 0x0000 0x03>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx_rx".
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For example
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dma-names = "tx_rx";
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flash-id:
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type: int
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description: |
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FLash ID number. This number, if defined, helps to select the right
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QSPI GPIO banks (defined as 'quadspi_bk[12]' in pinctrl property)
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to communicate with flash memory.
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For example
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flash-id = <2>;
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