153 lines
3.0 KiB
Plaintext
153 lines
3.0 KiB
Plaintext
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <freq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
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model = "sifive,FU740";
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clocks {
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coreclk: core-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(1000)>;
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};
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pclk: p-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(125125)>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "sifive,s7";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "okay";
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hlic: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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modeselect: rom@1000 {
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compatible = "sifive,modeselect0";
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reg = <0x1000 0x1000>;
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reg-names = "mem";
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};
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maskrom: rom@10000 {
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compatible = "sifive,maskrom0";
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reg = <0x10000 0x8000>;
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reg-names = "mem";
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};
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dtim: dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x1000000 0x2000>;
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reg-names = "mem";
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};
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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interrupts-extended = <&hlic 3 &hlic 7>;
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reg = <0x2000000 0x10000>;
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};
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l2lim: l2lim@8000000 {
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compatible = "sifive,l2lim0";
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reg = <0x8000000 0x200000>;
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reg-names = "mem";
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0x0c000000 0x00002000
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0x0c002000 0x001fe000
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0x0c200000 0x03e00000>;
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reg-names = "prio", "irq_en", "reg";
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riscv,max-priority = <7>;
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riscv,ndev = <52>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <39 1>;
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reg = <0x10010000 0x1000>;
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reg-names = "control";
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status = "disabled";
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};
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uart1: serial@10011000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <40 1>;
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reg = <0x10011000 0x1000>;
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reg-names = "control";
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status = "disabled";
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};
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spi0: spi@10040000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <41 1>;
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reg = <0x10040000 0x1000 0x20000000 0x10000000>;
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reg-names = "control", "mem";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@10041000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <42 1>;
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reg = <0x10041000 0x1000>;
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reg-names = "control";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@10050000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <43 1>;
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reg = <0x10050000 0x1000>;
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reg-names = "control";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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