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| README | ||
| ghrd_10m50da.dpf | ||
| ghrd_10m50da.qpf | ||
| ghrd_10m50da.qsf | ||
| ghrd_10m50da.qsys | ||
| ghrd_10m50da.qws | ||
| ghrd_10m50da.sof | ||
| ghrd_10m50da.sopcinfo | ||
| ghrd_10m50da_top.v | ||
| ghrd_timing.sdc | ||
| stp1.stp | ||
README
These files are a Nios II/F CPU design provided by Altera for evaluating Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C development board. You can find more information about this board here: https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html You will need the Quartus SDK in order to modify this CPU or flash it onto a supported device. The Lite version of Quartus may be obtained without charge from the following link: http://dl.altera.com/?edition=lite To flash this CPU, use the nios2-configure-sof tool: $ nios2-configure-sof ghrd_10m50da.sof The 'make flash' target will also package up the kernel and CPU into a single .pof file which will then put the image onto the device using quartus_pgm tool.