35 lines
827 B
C
35 lines
827 B
C
/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
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*/
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#ifndef SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
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#define SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
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#ifdef CONFIG_RISCV_SOC_OFFSETS
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/* Andes V5 specific registers. */
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#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, mxstatus); \
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GEN_OFFSET_SYM(soc_esf_t, ucode)
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#elif defined(CONFIG_SOC_ANDES_V5_PFT)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, mxstatus)
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#elif defined(CONFIG_SOC_ANDES_V5_HWDSP)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, ucode)
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#endif
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#endif /* CONFIG_RISCV_SOC_OFFSETS */
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#endif /* SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_*/
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