069d409b29
The Cortex-M7 CPU included in the STM32F7 SoCs has instruction and data caches that significantly boost the performances. Enable them during the SoC initialization. Note that the D-cache should only be enabled if it is disabled, to workaround CMSIS issue #331. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> |
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.. | ||
CMakeLists.txt | ||
Kconfig.defconfig.series | ||
Kconfig.defconfig.stm32f723xe | ||
Kconfig.defconfig.stm32f746xg | ||
Kconfig.defconfig.stm32f769xi | ||
Kconfig.series | ||
Kconfig.soc | ||
dts.fixup | ||
flash_registers.h | ||
gpio_registers.h | ||
linker.ld | ||
soc.c | ||
soc.h | ||
soc_gpio.c | ||
soc_registers.h |