35 lines
664 B
C
35 lines
664 B
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32F1 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <stm32_ll_system.h>
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#include <cmsis_core.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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#ifdef FLASH_ACR_PRFTBE
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/* Enable ART Accelerator prefetch */
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LL_FLASH_EnablePrefetch();
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#endif
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 8 MHz from HSI */
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SystemCoreClock = 8000000;
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}
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