375 lines
11 KiB
C
375 lines
11 KiB
C
/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <hal/nrf_gpio.h>
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BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) &&
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(NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) &&
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(NRF_PULL_UP == NRF_GPIO_PIN_PULLUP)),
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"nRF pinctrl pull settings do not match HAL values");
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#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
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#define NRF_DRIVE_COUNT (NRF_DRIVE_E0E1 + 1)
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#else
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#define NRF_DRIVE_COUNT (NRF_DRIVE_H0D1 + 1)
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#endif
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static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
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[NRF_DRIVE_S0S1] = NRF_GPIO_PIN_S0S1,
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[NRF_DRIVE_H0S1] = NRF_GPIO_PIN_H0S1,
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[NRF_DRIVE_S0H1] = NRF_GPIO_PIN_S0H1,
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[NRF_DRIVE_H0H1] = NRF_GPIO_PIN_H0H1,
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[NRF_DRIVE_D0S1] = NRF_GPIO_PIN_D0S1,
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[NRF_DRIVE_D0H1] = NRF_GPIO_PIN_D0H1,
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[NRF_DRIVE_S0D1] = NRF_GPIO_PIN_S0D1,
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[NRF_DRIVE_H0D1] = NRF_GPIO_PIN_H0D1,
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#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
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[NRF_DRIVE_E0E1] = NRF_GPIO_PIN_E0E1,
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#endif
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};
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/* value to indicate pin level doesn't need initialization */
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#define NO_WRITE UINT32_MAX
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#define PSEL_DISCONNECTED 0xFFFFFFFFUL
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart) || defined(CONFIG_NRFX_UART)
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#define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte) || defined(CONFIG_NRFX_UARTE)
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#include <hal/nrf_uarte.h>
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#define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) || defined(CONFIG_NRFX_SPI)
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#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) || defined(CONFIG_NRFX_SPIM)
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#include <hal/nrf_spim.h>
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#define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) || defined(CONFIG_NRFX_SPIS)
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#include <hal/nrf_spis.h>
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#if defined(NRF51)
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#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line
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#else
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#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line
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#endif
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twi) || defined(CONFIG_NRFX_TWI)
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#if !defined(TWI_PSEL_SCL_CONNECT_Pos)
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#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line
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#else
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#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line
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#endif
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim) || defined(CONFIG_NRFX_TWIM)
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#include <hal/nrf_twim.h>
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#define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_i2s) || defined(CONFIG_NRFX_I2S)
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#define NRF_PSEL_I2S(reg, line) ((NRF_I2S_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pdm) || defined(CONFIG_NRFX_PDM)
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#define NRF_PSEL_PDM(reg, line) ((NRF_PDM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm) || defined(CONFIG_NRFX_PWM)
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#define NRF_PSEL_PWM(reg, line) ((NRF_PWM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qdec) || defined(CONFIG_NRFX_QDEC)
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#define NRF_PSEL_QDEC(reg, line) ((NRF_QDEC_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qspi) || defined(CONFIG_NRFX_QSPI)
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#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
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#endif
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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nrf_gpio_pin_drive_t drive;
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uint8_t drive_idx = NRF_GET_DRIVE(pins[i]);
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uint32_t psel = NRF_GET_PIN(pins[i]);
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uint32_t write = NO_WRITE;
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nrf_gpio_pin_dir_t dir;
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nrf_gpio_pin_input_t input;
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if (drive_idx < ARRAY_SIZE(drive_modes)) {
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drive = drive_modes[drive_idx];
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} else {
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return -EINVAL;
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}
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if (psel == NRF_PIN_DISCONNECTED) {
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psel = PSEL_DISCONNECTED;
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}
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switch (NRF_GET_FUN(pins[i])) {
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#if defined(NRF_PSEL_UART)
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case NRF_FUN_UART_TX:
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NRF_PSEL_UART(reg, TXD) = psel;
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write = 1U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_UART_RX:
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NRF_PSEL_UART(reg, RXD) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_UART_RTS:
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NRF_PSEL_UART(reg, RTS) = psel;
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write = 1U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_UART_CTS:
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NRF_PSEL_UART(reg, CTS) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_UART) */
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#if defined(NRF_PSEL_SPIM)
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case NRF_FUN_SPIM_SCK:
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NRF_PSEL_SPIM(reg, SCK) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_SPIM_MOSI:
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NRF_PSEL_SPIM(reg, MOSI) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_SPIM_MISO:
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NRF_PSEL_SPIM(reg, MISO) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_SPIM) */
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#if defined(NRF_PSEL_SPIS)
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case NRF_FUN_SPIS_SCK:
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NRF_PSEL_SPIS(reg, SCK) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_SPIS_MOSI:
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NRF_PSEL_SPIS(reg, MOSI) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_SPIS_MISO:
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NRF_PSEL_SPIS(reg, MISO) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_SPIS_CSN:
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NRF_PSEL_SPIS(reg, CSN) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_SPIS) */
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#if defined(NRF_PSEL_TWIM)
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case NRF_FUN_TWIM_SCL:
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NRF_PSEL_TWIM(reg, SCL) = psel;
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if (drive == NRF_GPIO_PIN_S0S1) {
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/* Override the default drive setting with one
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* suitable for TWI/TWIM peripherals (S0D1).
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* This drive cannot be used always so that
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* users are able to select e.g. H0D1 or E0E1
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* in devicetree.
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*/
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drive = NRF_GPIO_PIN_S0D1;
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}
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_TWIM_SDA:
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NRF_PSEL_TWIM(reg, SDA) = psel;
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if (drive == NRF_GPIO_PIN_S0S1) {
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drive = NRF_GPIO_PIN_S0D1;
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}
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_TWIM) */
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#if defined(NRF_PSEL_I2S)
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case NRF_FUN_I2S_SCK_M:
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NRF_PSEL_I2S(reg, SCK) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_I2S_SCK_S:
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NRF_PSEL_I2S(reg, SCK) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_I2S_LRCK_M:
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NRF_PSEL_I2S(reg, LRCK) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_I2S_LRCK_S:
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NRF_PSEL_I2S(reg, LRCK) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_I2S_SDIN:
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NRF_PSEL_I2S(reg, SDIN) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_I2S_SDOUT:
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NRF_PSEL_I2S(reg, SDOUT) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_I2S_MCK:
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NRF_PSEL_I2S(reg, MCK) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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#endif /* defined(NRF_PSEL_I2S) */
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#if defined(NRF_PSEL_PDM)
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case NRF_FUN_PDM_CLK:
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NRF_PSEL_PDM(reg, CLK) = psel;
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write = 0U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_PDM_DIN:
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NRF_PSEL_PDM(reg, DIN) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_PDM) */
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#if defined(NRF_PSEL_PWM)
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case NRF_FUN_PWM_OUT0:
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NRF_PSEL_PWM(reg, OUT[0]) = psel;
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write = NRF_GET_INVERT(pins[i]);
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_PWM_OUT1:
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NRF_PSEL_PWM(reg, OUT[1]) = psel;
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write = NRF_GET_INVERT(pins[i]);
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_PWM_OUT2:
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NRF_PSEL_PWM(reg, OUT[2]) = psel;
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write = NRF_GET_INVERT(pins[i]);
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_PWM_OUT3:
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NRF_PSEL_PWM(reg, OUT[3]) = psel;
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write = NRF_GET_INVERT(pins[i]);
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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#endif /* defined(NRF_PSEL_PWM) */
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#if defined(NRF_PSEL_QDEC)
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case NRF_FUN_QDEC_A:
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NRF_PSEL_QDEC(reg, A) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_QDEC_B:
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NRF_PSEL_QDEC(reg, B) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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case NRF_FUN_QDEC_LED:
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NRF_PSEL_QDEC(reg, LED) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_QDEC) */
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#if defined(NRF_PSEL_QSPI)
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case NRF_FUN_QSPI_SCK:
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NRF_PSEL_QSPI(reg, SCK) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_QSPI_CSN:
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NRF_PSEL_QSPI(reg, CSN) = psel;
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write = 1U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_QSPI_IO0:
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NRF_PSEL_QSPI(reg, IO0) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_QSPI_IO1:
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NRF_PSEL_QSPI(reg, IO1) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_QSPI_IO2:
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NRF_PSEL_QSPI(reg, IO2) = psel;
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_QSPI_IO3:
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NRF_PSEL_QSPI(reg, IO3) = psel;
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write = 1U;
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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#endif /* defined(NRF_PSEL_QSPI) */
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can)
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/* Pin routing is controlled by secure domain, via UICR */
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case NRF_FUN_CAN_TX:
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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break;
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case NRF_FUN_CAN_RX:
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */
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default:
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return -ENOTSUP;
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}
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/* configure GPIO properties */
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if (psel != PSEL_DISCONNECTED) {
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uint32_t pin = psel;
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if (write != NO_WRITE) {
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nrf_gpio_pin_write(pin, write);
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}
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/* force input and disconnected buffer for low power */
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if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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}
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nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
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drive, NRF_GPIO_PIN_NOSENSE);
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#if NRF_GPIO_HAS_CLOCKPIN
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nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
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#endif
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}
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}
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return 0;
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}
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