62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/*
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* Copyright (c) 2020, NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <fsl_device_registers.h>
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static int mimxrt685_evk_init(void)
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{
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/* flexcomm1 and flexcomm3 are configured to loopback the TX signal to RX */
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) && \
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(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) && \
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CONFIG_I2S
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/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */
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SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) |
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SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Data in from Transmit I2S - Flexcomm 3 */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3);
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/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);
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#endif
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/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
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/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */
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SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
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#endif
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#endif
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#ifdef CONFIG_REBOOT
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/*
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* The sys_reboot API calls NVIC_SystemReset. On the RT685, the warm
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* reset will not complete correctly unless the ROM toggles the
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* flash reset pin. We can control this behavior using the OTP shadow
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* register for OPT word BOOT_CFG1
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*
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* Set FLEXSPI_RESET_PIN_ENABLE=1, FLEXSPI_RESET_PIN= PIO2_12
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*/
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OCOTP->OTP_SHADOW[97] = 0x314000;
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#endif /* CONFIG_REBOOT */
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return 0;
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}
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SYS_INIT(mimxrt685_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
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