126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <fsl_clock.h>
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#include <fsl_spc.h>
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#include <soc.h>
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/* Core clock frequency: 150MHz */
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#define CLOCK_INIT_CORE_CLOCK 960000000U
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#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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static int frdm_mcxa156_init(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL =
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(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL =
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(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
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RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
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RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
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RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
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RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
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RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
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RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO0);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
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RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO1);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
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RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO2);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
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RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO3);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
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RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_GateGPIO4);
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
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CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
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CLOCK_AttachClk(kFRO12M_to_LPUART0);
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#endif
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/* Set SystemCoreClock variable. */
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SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
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return 0;
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}
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SYS_INIT(frdm_mcxa156_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
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