418 lines
11 KiB
C
418 lines
11 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <nanokernel.h>
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#include <gpio.h>
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#include <gpio/gpio-dw.h>
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#include <board.h>
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#include <sys_io.h>
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define SWPORTB_DR 0x0c
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#define SWPORTB_DDR 0x10
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#define SWPORTC_DR 0x18
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#define SWPORTC_DDR 0x1c
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#define SWPORTD_DR 0x24
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#define SWPORTD_DDR 0x28
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#define INTEN 0x30
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#define INTMASK 0x34
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define INTSTATUS 0x40
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#define PORTA_DEBOUNCE 0x48
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#define PORTA_EOI 0x4c
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#define EXT_PORTA 0x50
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#define EXT_PORTB 0x54
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#define EXT_PORTC 0x58
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#define EXT_PORTD 0x5c
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#define INT_CLOCK_SYNC 0x60
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#define INT_BOTHEDGE 0x68
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#define BIT(n) (1UL << (n))
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static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
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{
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return sys_read32(base_addr + offset);
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}
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static inline void dw_write(uint32_t base_addr, uint32_t offset,
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uint32_t val)
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{
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sys_write32(val, base_addr + offset);
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}
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static void dw_set_bit(uint32_t base_addr, uint32_t offset,
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uint32_t bit, uint8_t value)
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{
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if (!value) {
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sys_clear_bit(base_addr + offset, bit);
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} else {
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sys_set_bit(base_addr + offset, bit);
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}
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}
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static inline void dw_interrupt_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint8_t flag_is_set;
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/* set as an input pin */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, 0);
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/* level or edge */
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flag_is_set = (flags & GPIO_INT_EDGE);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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/* Active low/high */
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flag_is_set = (flags & GPIO_INT_ACTIVE_HIGH);
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dw_set_bit(base_addr, INT_POLARITY, pin, flag_is_set);
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/* both edges */
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flag_is_set = (flags & GPIO_INT_DOUBLE_EDGE);
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if (flag_is_set) {
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dw_set_bit(base_addr, INT_BOTHEDGE, pin, flag_is_set);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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}
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/* use built-in debounce */
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flag_is_set = (flags & GPIO_INT_DEBOUNCE );
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dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, flag_is_set);
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/* level triggered int synchronous with clock */
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flag_is_set = (flags & GPIO_INT_CLOCK_SYNC );
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dw_set_bit(base_addr, INT_CLOCK_SYNC, pin, flag_is_set);
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dw_set_bit(base_addr, INTEN, pin, 1);
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}
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static inline void dw_pin_config(struct device *port,
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uint32_t pin, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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/* clear interrupt enable */
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dw_set_bit(base_addr, INTEN, pin, 0);
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/* set direction */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT)
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dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
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}
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static inline void dw_port_config(struct device *port, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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int i;
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for (i=0; i < config->bits; i++) {
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dw_pin_config(port, i, flags);
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}
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}
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static inline int gpio_config_dw(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -1;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_pin_config(port, pin, flags);
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} else {
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dw_port_config(port, flags);
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}
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return 0;
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}
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static inline int gpio_write_dw(struct device *port, int access_op,
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uint32_t pin, uint32_t value)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, SWPORTA_DR, pin, value);
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} else {
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dw_write(base_addr, SWPORTA_DR, value);
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}
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return 0;
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}
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static inline int gpio_read_dw(struct device *port, int access_op,
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uint32_t pin, uint32_t *value)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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*value = dw_read(base_addr, EXT_PORTA);
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if (GPIO_ACCESS_BY_PIN == access_op) {
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*value = !!(*value & BIT(pin));
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}
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return 0;
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}
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static inline int gpio_set_callback_dw(struct device *port,
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gpio_callback_t callback)
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{
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struct gpio_runtime_dw *context = port->driver_data;
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context->callback = callback;
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return 0;
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}
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static inline int gpio_enable_callback_dw(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_config_dw *config = port->config->config_info;
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struct gpio_runtime_dw *context = port->driver_data;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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context->enabled_callbacks |= BIT(pin);
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} else {
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context->port_callback = 1;
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}
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dw_write(base_addr, PORTA_EOI, BIT(pin));
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dw_set_bit(base_addr, INTMASK, pin, 0);
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return 0;
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}
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static inline int gpio_disable_callback_dw(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_config_dw *config = port->config->config_info;
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struct gpio_runtime_dw *context = port->driver_data;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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context->enabled_callbacks &= ~(BIT(pin));
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} else {
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context->port_callback = 0;
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}
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dw_set_bit(base_addr, INTMASK, pin, 1);
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return 0;
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}
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static inline int gpio_suspend_port_dw(struct device *port)
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{
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return 0;
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}
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static inline int gpio_resume_port_dw(struct device *port)
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{
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return 0;
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}
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void gpio_dw_isr(struct device *port)
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{
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struct gpio_runtime_dw *context = port->driver_data;
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint32_t enabled_int, int_status, bit;
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int_status = dw_read(base_addr, INTSTATUS);
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dw_write(base_addr, PORTA_EOI, -1);
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if (!context->callback) {
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return;
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}
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if (context->port_callback) {
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context->callback(port, int_status);
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return;
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}
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if (context->enabled_callbacks) {
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enabled_int = int_status & context->enabled_callbacks;
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for (bit = 0; bit < 32; bit++) {
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if (enabled_int & (1 << bit)) {
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context->callback(port, (1 << bit));
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}
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}
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}
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}
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static struct gpio_driver_api api_funcs = {
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.config = gpio_config_dw,
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.write = gpio_write_dw,
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.read = gpio_read_dw,
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.set_callback = gpio_set_callback_dw,
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.enable_callback = gpio_enable_callback_dw,
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.disable_callback = gpio_disable_callback_dw,
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.suspend = gpio_suspend_port_dw,
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.resume = gpio_resume_port_dw
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};
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#ifdef CONFIG_PCI
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static inline int gpio_dw_setup(struct device *dev)
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{
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struct gpio_config_dw *config = dev->config->config_info;
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pci_bus_scan_init();
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if (!pci_bus_scan(&config->pci_dev)) {
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return 0;
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}
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#ifdef CONFIG_PCI_ENUMERATION
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config->base_addr = config->pci_dev.addr;
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config->irq_num = config->pci_dev.irq;
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#endif
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pci_enable_regs(&config->pci_dev);
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pci_show(&config->pci_dev);
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return 1;
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}
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#else
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#define gpio_dw_setup(_unused_) (1)
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#endif /* CONFIG_PCI */
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int gpio_initialize_dw(struct device *port)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (!gpio_dw_setup(port)) {
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return DEV_NOT_CONFIG;
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}
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/* interrupts in sync with system clock */
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dw_set_bit(base_addr, INT_CLOCK_SYNC, 0, 1);
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/* mask and disable interrupts */
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dw_write(base_addr, INTMASK, ~(0));
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dw_write(base_addr, INTEN, 0);
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dw_write(base_addr, PORTA_EOI, ~(0));
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port->driver_api = &api_funcs;
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config->config_func(port);
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irq_enable(config->irq_num);
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return 0;
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}
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/* Bindings to the plaform */
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#if CONFIG_GPIO_DW_0
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void gpio_config_0_irq(struct device *port);
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struct gpio_config_dw gpio_config_dw_0 = {
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.base_addr = CONFIG_GPIO_DW_0_BASE_ADDR,
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.bits = CONFIG_GPIO_DW_0_BITS,
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.irq_num = CONFIG_GPIO_DW_0_IRQ,
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#if CONFIG_PCI
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.pci_dev.class = CONFIG_GPIO_DW_CLASS,
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.pci_dev.bus = CONFIG_GPIO_DW_0_BUS,
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.pci_dev.dev = CONFIG_GPIO_DW_0_DEV,
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.pci_dev.vendor_id = CONFIG_GPIO_DW_VENDOR_ID,
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.pci_dev.device_id = CONFIG_GPIO_DW_DEVICE_ID,
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.pci_dev.function = CONFIG_GPIO_DW_0_FUNCTION,
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.pci_dev.bar = CONFIG_GPIO_DW_0_BAR,
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#endif
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.config_func = gpio_config_0_irq
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};
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struct gpio_runtime_dw gpio_0_runtime;
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DECLARE_DEVICE_INIT_CONFIG(gpio_0, CONFIG_GPIO_DW_0_NAME,
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gpio_initialize_dw, &gpio_config_dw_0);
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pure_init(gpio_0, &gpio_0_runtime);
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IRQ_CONNECT_STATIC(gpio_dw_0, CONFIG_GPIO_DW_0_IRQ,
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CONFIG_GPIO_DW_0_PRI, gpio_dw_isr_0, 0);
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void gpio_config_0_irq(struct device *port)
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{
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struct gpio_config_dw *config = port->config->config_info;
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IRQ_CONFIG(gpio_dw_0, config->irq_num);
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}
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void gpio_dw_isr_0(void *unused)
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{
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gpio_dw_isr(&__initconfig_gpio_01);
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}
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#endif /* CONFIG_GPIO_DW_0 */
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#if CONFIG_GPIO_DW_1
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void gpio_config_1_irq(struct device *port);
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struct gpio_config_dw gpio_config_dw_1 = {
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.base_addr = CONFIG_GPIO_DW_1_BASE_ADDR,
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.bits = CONFIG_GPIO_DW_1_BITS,
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.irq_num = CONFIG_GPIO_DW_1_IRQ,
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#if CONFIG_PCI
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.pci_dev.class = CONFIG_GPIO_DW_CLASS,
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.pci_dev.bus = CONFIG_GPIO_DW_1_BUS,
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.pci_dev.dev = CONFIG_GPIO_DW_1_DEV,
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.pci_dev.vendor_id = CONFIG_GPIO_DW_VENDOR_ID,
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.pci_dev.device_id = CONFIG_GPIO_DW_DEVICE_ID,
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.pci_dev.function = CONFIG_GPIO_DW_1_FUNCTION,
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.pci_dev.bar = CONFIG_GPIO_DW_1_BAR,
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#endif
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.config_func = gpio_config_1_irq
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};
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struct gpio_runtime_dw gpio_1_runtime;
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DECLARE_DEVICE_INIT_CONFIG(gpio_1, CONFIG_GPIO_DW_1_NAME,
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gpio_initialize_dw, &gpio_config_dw_1);
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pure_init(gpio_1, &gpio_1_runtime);
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IRQ_CONNECT_STATIC(gpio_dw_1, CONFIG_GPIO_DW_1_IRQ,
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CONFIG_GPIO_DW_1_PRI, gpio_dw_isr_1, 0);
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void gpio_config_1_irq(struct device *port)
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{
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struct gpio_config_dw *config = port->config->config_info;
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IRQ_CONFIG(gpio_dw_1, config->irq_num);
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}
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void gpio_dw_isr_1(void *unused)
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{
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gpio_dw_isr(&__initconfig_gpio_11);
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}
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#endif /* CONFIG_GPIO_DW_1 */
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