365 lines
12 KiB
C
365 lines
12 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stddef.h>
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#ifndef _MEC172X_PCR_H
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#define _MEC172X_PCR_H
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#define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00u
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#define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04u
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#define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08u
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#define MCHP_PCR_OSC_ID_OFS 0x0cu
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#define MCHP_PCR_PRS_OFS 0x10u
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#define MCHP_PCR_PR_CTRL_OFS 0x14u
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#define MCHP_PCR_SYS_RESET_OFS 0x18u
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#define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1cu
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#define MCHP_PCR_SLP_EN0_OFS 0x30u
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#define MCHP_PCR_SLP_EN1_OFS 0x34u
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#define MCHP_PCR_SLP_EN2_OFS 0x38u
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#define MCHP_PCR_SLP_EN3_OFS 0x3cu
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#define MCHP_PCR_SLP_EN4_OFS 0x40u
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#define MCHP_PCR_CLK_REQ0_OFS 0x50u
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#define MCHP_PCR_CLK_REQ1_OFS 0x54u
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#define MCHP_PCR_CLK_REQ2_OFS 0x58u
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#define MCHP_PCR_CLK_REQ3_OFS 0x5cu
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#define MCHP_PCR_CLK_REQ4_OFS 0x60u
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#define MCHP_PCR_PERIPH_RST0_OFS 0x70u
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#define MCHP_PCR_PERIPH_RST1_OFS 0x74u
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#define MCHP_PCR_PERIPH_RST2_OFS 0x78u
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#define MCHP_PCR_PERIPH_RST3_OFS 0x7cu
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#define MCHP_PCR_PERIPH_RST4_OFS 0x80u
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#define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84u
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#define MCHP_PCR_VBAT_SRST_OFS 0x88u
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#define MCHP_PCR_CLK32K_SRC_VTR_OFS 0x8cu
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#define MCHP_PCR_CNT32K_PER_OFS 0xc0u
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#define MCHP_PCR_CNT32K_PULSE_HI_OFS 0xc4u
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#define MCHP_PCR_CNT32K_PER_MIN_OFS 0xc8u
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#define MCHP_PCR_CNT32K_PER_MAX_OFS 0xccu
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#define MCHP_PCR_CNT32K_DV_OFS 0xd0u
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#define MCHP_PCR_CNT32K_DV_MAX_OFS 0xd4u
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#define MCHP_PCR_CNT32K_VALID_OFS 0xd8u
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#define MCHP_PCR_CNT32K_VALID_MIN_OFS 0xdcu
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#define MCHP_PCR_CNT32K_CTRL_OFS 0xe0u
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#define MCHP_PCR_CLK32K_MON_ISTS_OFS 0xe4u
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#define MCHP_PCR_CLK32K_MON_IEN_OFS 0xe8u
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/*
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* MEC172x PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers.
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* CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
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* clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx
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* into light or heavy sleep.
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* SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
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* peripherals PCR CLK_REQ bit is 0.
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* RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
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* must be unlocked by writing the unlock code to PCR Peripheral Reset Lock
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* register.
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* SLP_EN usage is:
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* Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as
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* these IP do not implement internal clock gating.
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* When firmware wants to enter light or heavy sleep.
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* Configure wake up source(s)
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* Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with
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* SLEEP_ALL bit = 1.
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* Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
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* Cortex-M4 will assert sleep signal to PCR block.
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* PCR HW will spin until all CLK_REQ==0
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* PCR will then turn off clocks based on light/heavy sleep.
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*
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* RST_EN usage is:
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* Save and disable maskable interrupts
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* Write unlock code to PCR Peripheral Reset Lock
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* Write bit patterns to one or more of PCR RST_EN[0, 4] registers
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* Selected peripherals will be reset.
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* Write lock code to PCR Peripheral Reset Lock.
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* Restore interrupts.
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*/
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#define MCHP_MAX_PCR_SCR_REGS 5u
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/* VTR Powered PCR registers */
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#define MCHP_PCR_SLP(bitpos) BIT(bitpos)
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/* PCR System Sleep Control */
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#define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109u
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#define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0)
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#define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3)
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/*
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* bit[8] can be used to prevent entry to heavy sleep unless the
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* PLL is locked.
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* bit[8]==0 (POR default) system will allow entry to light or heavy
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* sleep if and only if PLL is locked.
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* bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
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*/
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#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK BIT(8)
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/* Assert all peripheral sleep enables once CPU asserts its sleep signal */
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#define MCHP_PCR_SYS_SLP_LIGHT BIT(3)
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#define MCHP_PCR_SYS_SLP_HEAVY (BIT(3) | BIT(0))
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/*
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* PCR Process Clock Control
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* Divides 96MHz clock to ARM Cortex-M4 core including
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* SysTick and NVIC.
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*/
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#define MCHP_PCR_PROC_CLK_CTRL_MASK GENMASK(7, 0)
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#define MCHP_PCR_PROC_CLK_CTRL_96MHZ 1
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#define MCHP_PCR_PROC_CLK_CTRL_48MHZ 2
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#define MCHP_PCR_PROC_CLK_CTRL_24MHZ 4
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#define MCHP_PCR_PROC_CLK_CTRL_12MHZ 8
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#define MCHP_PCR_PROC_CLK_CTRL_6MHZ 16
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#define MCHP_PCR_PROC_CLK_CTRL_2MHZ 48
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#define MCHP_PCR_PROC_CLK_CTRL_DFLT MCHP_PCR_PROC_CLK_CTRL_24MHZ
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/* PCR Slow Clock Control. Clock divider for 100KHz clock domain */
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#define MCHP_PCR_SLOW_CLK_CTRL_MASK GENMASK(9, 0)
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#define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1e0u
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/* PCR Oscillator ID register (Read-Only) */
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#define MCHP_PCR_OSC_ID_MASK GENMASK(8, 0)
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#define MCHP_PCR_OSC_ID_PLL_LOCK BIT(8)
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/* PCR Power Reset Status Register */
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#define MCHP_PCR_PRS_MASK \
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(GENMASK(11, 10) | GENMASK(8, 2))
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#define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO BIT(2)
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#define MCHP_PCR_PRS_HOST_RESET_STATE_RO BIT(3)
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#define MCHP_PCR_PRS_VTR_RST_RWC BIT(4)
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#define MCHP_PCR_PRS_VBAT_RST_RWC BIT(5)
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#define MCHP_PCR_PRS_RST_SYS_RWC BIT(6)
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#define MCHP_PCR_PRS_JTAG_RST_RO BIT(7)
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#define MCHP_PCR_PRS_WDT_EVENT_RWC BIT(8)
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#define MCHP_PCR_PRS_32K_ACTIVE_RO BIT(10)
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#define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO BIT(11)
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/* PCR Power Reset Control Register */
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#define MCHP_PCR_PR_CTRL_MASK (BIT(8) | BIT(0))
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#define MCHP_PCR_PR_CTRL_PWR_INV BIT(0)
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#define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST 0u
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#define MCHP_PCR_PR_CTRL_USE_PCI_RST BIT(8)
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/* PCR System Reset Register */
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#define MCHP_PCR_SYS_RESET_MASK BIT(8)
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#define MCHP_PCR_SYS_RESET_NOW BIT(8)
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/* Turbo Clock Register */
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#define MCHP_PCR_TURBO_CLK_MASK BIT(2)
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#define MCHP_PCR_TURBO_CLK_96M BIT(2)
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/*
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* Sleep Enable Reg 0 (Offset +30h)
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* Clock Required Reg 0 (Offset +50h)
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* Reset Enable Reg 0 (Offset +70h)
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*/
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#define MCHP_PCR0_JTAG_STAP_POS 0
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#define MCHP_PCR0_OTP_POS 1
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#define MCHP_PCR0_ISPI_EMC_POS 2
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/*
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* Sleep Enable Reg 1 (Offset +34h)
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* Clock Required Reg 1 (Offset +54h)
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* Reset Enable Reg 1 (Offset +74h)
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*/
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#define MCHP_PCR1_ECIA_POS 0
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#define MCHP_PCR1_PECI_POS 1
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#define MCHP_PCR1_TACH0_POS 2
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#define MCHP_PCR1_PWM0_POS 4
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#define MCHP_PCR1_PMC_POS 5
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#define MCHP_PCR1_DMA_POS 6
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#define MCHP_PCR1_TFDP_POS 7
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#define MCHP_PCR1_CPU_POS 8
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#define MCHP_PCR1_WDT_POS 9
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#define MCHP_PCR1_SMB0_POS 10
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#define MCHP_PCR1_TACH1_POS 11
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#define MCHP_PCR1_TACH2_POS 12
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#define MCHP_PCR1_TACH3_POS 13
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#define MCHP_PCR1_PWM1_POS 20
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#define MCHP_PCR1_PWM2_POS 21
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#define MCHP_PCR1_PWM3_POS 22
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#define MCHP_PCR1_PWM4_POS 23
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#define MCHP_PCR1_PWM5_POS 24
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#define MCHP_PCR1_PWM6_POS 25
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#define MCHP_PCR1_PWM7_POS 26
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#define MCHP_PCR1_PWM8_POS 27
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#define MCHP_PCR1_ECS_POS 29
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#define MCHP_PCR1_B16TMR0_POS 30
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#define MCHP_PCR1_B16TMR1_POS 31
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/*
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* Sleep Enable Reg 2 (Offset +38h)
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* Clock Required Reg 2 (Offset +58h)
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* Reset Enable Reg 2 (Offset +78h)
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*/
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#define MCHP_PCR2_EMI0_POS 0
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#define MCHP_PCR2_UART0_POS 1
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#define MCHP_PCR2_UART1_POS 2
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#define MCHP_PCR2_GCFG_POS 12
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#define MCHP_PCR2_ACPI_EC0_POS 13
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#define MCHP_PCR2_ACPI_EC1_POS 14
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#define MCHP_PCR2_ACPI_PM1_POS 15
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#define MCHP_PCR2_KBC_POS 16
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#define MCHP_PCR2_MBOX_POS 17
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#define MCHP_PCR2_RTC_POS 18
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#define MCHP_PCR2_ESPI_POS 19
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#define MCHP_PCR2_SCR32_POS 20
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#define MCHP_PCR2_ACPI_EC2_POS 21
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#define MCHP_PCR2_ACPI_EC3_POS 22
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#define MCHP_PCR2_ACPI_EC4_POS 23
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#define MCHP_PCR2_P80BD_POS 25
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#define MCHP_PCR2_ESPI_SAF_POS 27
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#define MCHP_PCR2_GLUE_POS 29
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/*
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* Sleep Enable Reg 3 (Offset +3Ch)
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* Clock Required Reg 3 (Offset +5Ch)
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* Reset Enable Reg 3 (Offset +7Ch)
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*/
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#define MCHP_PCR3_ADC_POS 3
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#define MCHP_PCR3_PS2_0_POS 5
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#define MCHP_PCR3_GPSPI0_POS 9
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#define MCHP_PCR3_HTMR0_POS 10
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#define MCHP_PCR3_KEYSCAN_POS 11
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#define MCHP_PCR3_RPMFAN0_POS 12
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#define MCHP_PCR3_SMB1_POS 13
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#define MCHP_PCR3_SMB2_POS 14
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#define MCHP_PCR3_SMB3_POS 15
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#define MCHP_PCR3_LED0_POS 16
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#define MCHP_PCR3_LED1_POS 17
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#define MCHP_PCR3_LED2_POS 18
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#define MCHP_PCR3_BCL0_POS 19
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#define MCHP_PCR3_SMB4_POS 20
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#define MCHP_PCR3_B16TMR2_POS 21
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#define MCHP_PCR3_B16TMR3_POS 22
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#define MCHP_PCR3_B32TMR0_POS 23
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#define MCHP_PCR3_B32TMR1_POS 24
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#define MCHP_PCR3_LED3_POS 25
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#define MCHP_PCR3_CRYPTO_POS 26
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#define MCHP_PCR3_HTMR1_POS 29
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#define MCHP_PCR3_CCT_POS 30
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#define MCHP_PCR3_PWM9_POS 31
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#define MCHP_PCR3_CRYPTO_MASK BIT(MCHP_PCR3_CRYPTO_POS)
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/*
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* Sleep Enable Reg 4 (Offset +40h)
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* Clock Required Reg 4 (Offset +60h)
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* Reset Enable Reg 4 (Offset +80h)
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*/
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#define MCHP_PCR4_PWM10_POS 0
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#define MCHP_PCR4_PWM11_POS 1
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#define MCHP_CTMR0_POS 2
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#define MCHP_CTMR1_POS 3
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#define MCHP_CTMR2_POS 4
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#define MCHP_CTMR3_POS 5
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#define MCHP_PCR4_RTMR_POS 6
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#define MCHP_PCR4_RPMFAN1_POS 7
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#define MCHP_PCR4_QMSPI_POS 8
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#define MCHP_PCR4_RCID0_POS 10
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#define MCHP_PCR4_RCID1_POS 11
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#define MCHP_PCR4_RCID2_POS 12
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#define MCHP_PCR4_PHOT_POS 13
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#define MCHP_PCR4_EEPROM_POS 14
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#define MCHP_PCR4_SPIP_POS 16
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#define MCHP_PCR4_GPSPI1_POS 22
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/* Reset Enable Lock (Offset +84h) */
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#define MCHP_PCR_RSTEN_UNLOCK 0xa6382d4cu
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#define MCHP_PCR_RSTEN_LOCK 0xa6382d4du
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/* VBAT Soft Reset (Offset +88h) */
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#define MCHP_PCR_VBSR_MASK BIT(0)
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#define MCHP_PCR_VBSR_EN BIT(0) /* self clearing */
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/* VTR Source 32 KHz Clock (Offset +8Ch) */
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#define MCHP_PCR_VTR_32K_SRC_MASK GENMASK(1, 0)
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#define MCHP_PCR_VTR_32K_SRC_SILOSC 0u
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#define MCHP_PCR_VTR_32K_SRC_XTAL BIT(0)
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#define MCHP_PCR_VTR_32K_SRC_PIN BIT(1)
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#define MCHP_PCR_VTR_32K_SRC_NONE (BIT(0) | BIT(1))
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/*
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* Clock monitor 32KHz period counter (Offset +C0h, RO)
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* Clock monitor 32KHz high counter (Offset +C4h, RO)
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* Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
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* Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
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* Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
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* Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
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*/
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#define MCHP_PCR_CLK32M_CNT_MASK GENMASK(15, 0)
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/*
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* Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
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* Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
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*/
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#define MCHP_PCR_CLK32M_VALID_CNT_MASK GENMASK(7, 0)
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/* Clock monitor control register (Offset +0xE0, RW) */
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#define MCHP_PCR_CLK32M_CTRL_MASK (BIT(24) | BIT(4) | GENMASK(2, 0))
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#define MCHP_PCR_CLK32M_CTRL_PER_EN BIT(0)
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#define MCHP_PCR_CLK32M_CTRL_DC_EN BIT(1)
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#define MCHP_PCR_CLK32M_CTRL_VAL_EN BIT(2)
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#define MCHP_PCR_CLK32M_CTRL_SRC_SO BIT(4)
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#define MCHP_PCR_CLK32M_CTRL_CLR_CNT BIT(24)
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/* Clock monitor interrupt status (Offset +0xE4, R/W1C) */
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#define MCHP_PCR_CLK32M_ISTS_MASK GENMASK(6, 0)
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#define MCHP_PCR_CLK32M_ISTS_PULSE_RDY BIT(0)
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#define MCHP_PCR_CLK32M_ISTS_PASS_PER BIT(1)
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#define MCHP_PCR_CLK32M_ISTS_PASS_DC BIT(2)
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#define MCHP_PCR_CLK32M_ISTS_FAIL BIT(3)
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#define MCHP_PCR_CLK32M_ISTS_STALL BIT(4)
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#define MCHP_PCR_CLK32M_ISTS_VALID BIT(5)
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#define MCHP_PCR_CLK32M_ISTS_UNWELL BIT(6)
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/* Clock monitor interrupt enable (Offset +0xE8, RW) */
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#define MCHP_PCR_CLK32M_IEN_MASK GENMASK(6, 0)
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#define MCHP_PCR_CLK32M_IEN_PULSE_RDY BIT(0)
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#define MCHP_PCR_CLK32M_IEN_PASS_PER BIT(1)
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#define MCHP_PCR_CLK32M_IEN_PASS_DC BIT(2)
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#define MCHP_PCR_CLK32M_IEN_FAIL BIT(3)
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#define MCHP_PCR_CLK32M_IEN_STALL BIT(4)
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#define MCHP_PCR_CLK32M_IEN_VALID BIT(5)
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#define MCHP_PCR_CLK32M_IEN_UNWELL BIT(6)
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/* PCR 32KHz clock monitor uses 48 MHz for all counters */
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#define MCHP_PCR_CLK32M_CLOCK 48000000u
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struct pcr_regs {
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volatile uint32_t SYS_SLP_CTRL;
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volatile uint32_t PROC_CLK_CTRL;
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volatile uint32_t SLOW_CLK_CTRL;
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volatile uint32_t OSC_ID;
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volatile uint32_t PWR_RST_STS;
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volatile uint32_t PWR_RST_CTRL;
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volatile uint32_t SYS_RST;
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volatile uint32_t TURBO_CLK;
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volatile uint32_t TEST20;
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uint32_t RSVD1[3];
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volatile uint32_t SLP_EN[5];
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uint32_t RSVD2[3];
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volatile uint32_t CLK_REQ[5];
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uint32_t RSVD3[3];
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volatile uint32_t RST_EN[5];
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volatile uint32_t RST_EN_LOCK;
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volatile uint32_t VBAT_SRST;
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volatile uint32_t CLK32K_SRC_VTR;
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volatile uint32_t TEST90;
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uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
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volatile uint32_t CNT32K_PER;
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volatile uint32_t CNT32K_PULSE_HI;
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volatile uint32_t CNT32K_PER_MIN;
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volatile uint32_t CNT32K_PER_MAX;
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volatile uint32_t CNT32K_DV;
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volatile uint32_t CNT32K_DV_MAX;
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volatile uint32_t CNT32K_VALID;
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volatile uint32_t CNT32K_VALID_MIN;
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volatile uint32_t CNT32K_CTRL;
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volatile uint32_t CLK32K_MON_ISTS;
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volatile uint32_t CLK32K_MON_IEN;
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};
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#endif /* #ifndef _MEC172X_PCR_H */
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