366 lines
9.8 KiB
C
366 lines
9.8 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC172X_ESPI_VW_H
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#define _MEC172X_ESPI_VW_H
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#include <stdint.h>
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#include <stddef.h>
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/* Master to Slave VW register: 96-bit (3 32 bit registers) */
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/* 32-bit word 0 (bits[31:0]) */
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#define ESPI_M2SW0_OFS 0u
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#define ESPI_M2SW0_IDX_POS 0
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#define ESPI_M2SW0_IDX_MASK 0xffu
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#define ESPI_M2SW0_MTOS_SRC_POS 8u
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#define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u
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#define ESPI_M2SW0_MTOS_SRC_MASK 0x300u
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#define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
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#define ESPI_M2SW0_MTOS_SRC_SYS_RST 0x100u
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#define ESPI_M2SW0_MTOS_SRC_SIO_RST 0x200u
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#define ESPI_M2SW0_MTOS_SRC_PLTRST 0x300u
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#define ESPI_M2SW0_MTOS_STATE_POS 12u
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#define ESPI_M2SW0_MTOS_STATE_MASK0 0x0fu
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#define ESPI_M2SW0_MTOS_STATE_MASK 0xf000u
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/* 32-bit word 1 (bits[63:32]) */
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#define ESPI_M2SW1_OFS 4u
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#define ESPI_M2SW1_SRC0_SEL_POS 0
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#define ESPI_M2SW1_SRC_SEL_MASK0 0x0fu
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#define ESPI_M2SW1_SRC0_SEL_MASK 0x0fu
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#define ESPI_M2SW1_SRC1_SEL_POS 8
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#define ESPI_M2SW1_SRC1_SEL_MASK 0x0f00u
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#define ESPI_M2SW1_SRC2_SEL_POS 16
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#define ESPI_M2SW1_SRC2_SEL_MASK 0x0f0000u
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#define ESPI_M2SW1_SRC3_SEL_POS 24
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#define ESPI_M2SW1_SRC3_SEL_MASK 0x0f000000u
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/* 0 <= n < 4 */
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#define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
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#define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
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#define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
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/* 32-bit word 2 (bits[95:64]) */
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#define ESPI_M2SW2_OFS 8u
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#define ESPI_M2SW2_SRC_MASK0 0x0fu
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#define ESPI_M2SW2_SRC0_POS 0
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#define ESPI_M2SW2_SRC0_MASK 0x0fu
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#define ESPI_M2SW2_SRC1_POS 8u
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#define ESPI_M2SW2_SRC1_MASK 0x0f00u
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#define ESPI_M2SW2_SRC2_POS 16u
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#define ESPI_M2SW2_SRC2_MASK 0x0f0000u
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#define ESPI_M2SW2_SRC3_POS 24u
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#define ESPI_M2SW2_SRC3_MASK 0x0f000000u
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/* 0 <= n < 4 */
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#define ESPI_M2SW2_SRC_POS(n) ((n) * 8u)
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#define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xfu, ((n) * 8u))
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#define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
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/*
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* Zero based values used for above SRC_SEL fields.
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* These values select the interrupt sensitivity for the VWire.
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* Example: Set SRC1 to Level High
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*
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* r = read MSVW1 register
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* r &= ESPI_M2SW1_SRC_SEL_MASK(1)
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* r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI)
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* write r to MSVW1 register
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*/
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#define ESPI_IRQ_SEL_LVL_LO 0
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#define ESPI_IRQ_SEL_LVL_HI 1
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#define ESPI_IRQ_SEL_DIS 4
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/* NOTE: Edge trigger modes allow VWires to wake from deep sleep */
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#define ESPI_IRQ_SEL_REDGE 0x0du
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#define ESPI_IRQ_SEL_FEDGE 0x0eu
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#define ESPI_IRQ_SEL_BEDGE 0x0fu
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/* Slave to Master VW register: 64-bit (2 32 bit registers) */
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/* 32-bit word 0 (bits[31:0]) */
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#define ESPI_S2MW0_OFS 0
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#define ESPI_S2MW0_IDX_POS 0
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#define ESPI_S2MW0_IDX_MASK 0xffu
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#define ESPI_S2MW0_STOM_POS 8u
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#define ESPI_S2MW0_STOM_SRC_POS 8u
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#define ESPI_S2MW0_STOM_MASK0 0xf3u
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#define ESPI_S2MW0_STOM_MASK 0xf300u
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#define ESPI_S2MW0_STOM_SRC_MASK0 0x03u
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#define ESPI_S2MW0_STOM_SRC_MASK 0x0300u
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#define ESPI_S2MW0_STOM_SRC_ESPI_RST 0u
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#define ESPI_S2MW0_STOM_SRC_SYS_RST 0x0100u
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#define ESPI_S2MW0_STOM_SRC_SIO_RST 0x0200u
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#define ESPI_S2MW0_STOM_SRC_PLTRST 0x0300u
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#define ESPI_S2MW0_STOM_STATE_POS 12u
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#define ESPI_S2MW0_STOM_STATE_MASK0 0x0fu
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#define ESPI_S2MW0_STOM_STATE_MASK 0x0f000u
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#define ESPI_S2MW0_CHG0_POS 16u
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#define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS)
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#define ESPI_S2MW0_CHG1_POS 17u
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#define ESPI_S2MW0_CHG1 BIT(ESPI_S2MW0_CHG1_POS)
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#define ESPI_S2MW0_CHG2_POS 18u
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#define ESPI_S2MW0_CHG2 BIT(ESPI_S2MW0_CHG2_POS)
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#define ESPI_S2MW0_CHG3_POS 19u
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#define ESPI_S2MW0_CHG3 BIT(ESPI_S2MW0_CHG3_POS)
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#define ESPI_S2MW0_CHG_ALL_POS 16u
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#define ESPI_S2MW0_CHG_ALL_MASK0 0x0fu
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#define ESPI_S2MW0_CHG_ALL_MASK 0x0f0000u
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/* 0 <= n < 4 */
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#define ESPI_S2MW1_CHG_POS(n) ((n) + 16u)
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#define ESPI_S2MW1_CHG(v, n) \
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(((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01)
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/* 32-bit word 1 (bits[63:32]) */
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#define ESPI_S2MW1_OFS 4u
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#define ESPI_S2MW1_SRC0_POS 0u
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#define ESPI_S2MW1_SRC0 BIT(ESPI_S2MW1_SRC0_POS)
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#define ESPI_S2MW1_SRC1_POS 8u
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#define ESPI_S2MW1_SRC1 BIT(ESPI_S2MW1_SRC1_POS)
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#define ESPI_S2MW1_SRC2_POS 16u
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#define ESPI_S2MW1_SRC2 BIT(ESPI_S2MW1_SRC2_POS)
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#define ESPI_S2MW1_SRC3_POS 24u
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#define ESPI_S2MW1_SRC3 BIT(ESPI_S2MW1_SRC3_POS)
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/* 0 <= n < 4 */
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#define ESPI_S2MW1_SRC_POS(n) SHLU32((n), 3)
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#define ESPI_S2MW1_SRC(v, n) \
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SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n)))
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/**
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* @brief eSPI Virtual Wires (ESPI_VW)
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*/
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#define ESPI_MSVW_IDX_MAX 10u
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#define ESPI_SMVW_IDX_MAX 10u
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#define ESPI_NUM_MSVW 11u
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#define ESPI_NUM_SMVW 11u
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/*
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* ESPI MSVW interrupts
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* GIRQ24 contains MSVW 0 - 6
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* GIRQ25 contains MSVW 7 - 10
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*/
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#define MEC_ESPI_MSVW_NUM_GIRQS 2u
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/* Master-to-Slave VW byte indices(offsets) */
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#define MSVW_INDEX_OFS 0u
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#define MSVW_MTOS_OFS 1u
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#define MSVW_SRC0_ISEL_OFS 4u
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#define MSVW_SRC1_ISEL_OFS 5u
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#define MSVW_SRC2_ISEL_OFS 6u
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#define MSVW_SRC3_ISEL_OFS 7u
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#define MSVW_SRC0_OFS 8u
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#define MSVW_SRC1_OFS 9u
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#define MSVW_SRC2_OFS 10u
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#define MSVW_SRC3_OFS 11u
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/* Slave-to-Master VW byte indices(offsets) */
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#define SMVW_INDEX_OFS 0u
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#define SMVW_STOM_OFS 1u
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#define SMVW_CHANGED_OFS 2u
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#define SMVW_SRC0_OFS 4u
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#define SMVW_SRC1_OFS 5u
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#define SMVW_SRC2_OFS 6u
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#define SMVW_SRC3_OFS 7u
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/* Master-to-Slave Virtual Wire 96-bit register */
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#define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
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#define MEC_MSVW_SRC1_IRQ_SEL_POS 8u
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#define MEC_MSVW_SRC2_IRQ_SEL_POS 16u
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#define MEC_MSVW_SRC3_IRQ_SEL_POS 24u
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#define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0fu
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#define MEC_MSVW_SRC0_IRQ_SEL_MASK \
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SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC0_IRQ_SEL_POS)
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#define MEC_MSVW_SRC1_IRQ_SEL_MASK \
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SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC1_IRQ_SEL_POS)
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#define MEC_MSVW_SRC2_IRQ_SEL_MASK \
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SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC2_IRQ_SEL_POS)
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#define MEC_MSVW_SRC3_IRQ_SEL_MASK \
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SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC3_IRQ_SEL_POS)
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#define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00u
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#define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01u
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#define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04u
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#define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0du
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#define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0eu
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#define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0fu
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/*
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* 0 <= src <= 3
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* isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ...
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*/
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#define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) \
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((uint32_t)(isel) << ((src) * 8u))
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#define MEC_MSVW_SRC0_POS 0u
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#define MEC_MSVW_SRC1_POS 8u
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#define MEC_MSVW_SRC2_POS 16u
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#define MEC_MSVW_SRC3_POS 24u
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#define MEC_MSVW_SRC_MASK0 0x01u
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#define MEC_MSVW_SRC0_MASK BIT(0)
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#define MEC_MSVW_SRC1_MASK BIT(8)
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#define MEC_MSVW_SRC2_MASK BIT(16)
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#define MEC_MSVW_SRC3_MASK BIT(24)
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/*
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* 0 <= src <= 3
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* val = 0 or 1
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*/
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#define MEC_MSVW_SRC_VAL(src, val) \
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((uint32_t)(val & 0x01u) << ((src) * 8u))
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/* Slave-to-Master Virtual Wire 64-bit register */
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/* MSVW helper inline functions */
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/* Interfaces to any C modules */
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum espi_msvw_src {
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MSVW_SRC0 = 0u,
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MSVW_SRC1,
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MSVW_SRC2,
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MSVW_SRC3
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};
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enum espi_smvw_src {
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SMVW_SRC0 = 0u,
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SMVW_SRC1,
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SMVW_SRC2,
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SMVW_SRC3
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};
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enum espi_msvw_irq_sel {
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MSVW_IRQ_SEL_LVL_LO = 0x00u,
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MSVW_IRQ_SEL_LVL_HI = 0x01u,
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MSVW_IRQ_SEL_DIS = 0x04u,
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MSVW_IRQ_SEL_EDGE_FALL = 0x0du,
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MSVW_IRQ_SEL_EDGE_RISE = 0x0eu,
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MSVW_IRQ_SEL_EDGE_BOTH = 0x0fu
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};
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/* Used for both MSVW MTOS and SMVW STOM fields */
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enum espi_vw_rst_src {
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VW_RST_SRC_ESPI_RESET = 0u,
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VW_RST_SRC_SYS_RESET,
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VW_RST_SRC_SIO_RESET,
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VW_RST_SRC_PLTRST,
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};
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enum espi_msvw_byte_idx {
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MSVW_BI_INDEX = 0,
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MSVW_BI_MTOS,
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MSVW_BI_RSVD2,
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MSVW_BI_RSVD3,
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MSVW_BI_IRQ_SEL0,
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MSVW_BI_IRQ_SEL1,
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MSVW_BI_IRQ_SEL2,
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MSVW_BI_IRQ_SEL3,
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MSVW_BI_SRC0,
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MSVW_BI_SRC1,
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MSVW_BI_SRC2,
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MSVW_BI_SRC3,
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MSVW_IDX_MAX
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};
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enum espi_smvw_byte_idx {
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SMVW_BI_INDEX = 0,
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SMVW_BI_STOM,
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SMVW_BI_SRC_CHG,
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SMVW_BI_RSVD3,
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SMVW_BI_SRC0,
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SMVW_BI_SRC1,
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SMVW_BI_SRC2,
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SMVW_BI_SRC3,
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SMVW_IDX_MAX
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};
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/** @brief eSPI 96-bit Host-to-Target Virtual Wire register */
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struct espi_msvw_reg {
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volatile uint8_t INDEX;
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volatile uint8_t MTOS;
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uint8_t RSVD1[2];
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volatile uint32_t SRC_IRQ_SEL;
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volatile uint32_t SRC;
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};
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/** @brief eSPI 96-bit Host-to-Target Virtual Wire register as bytes */
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struct espi_msvwb_reg {
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volatile uint8_t HTVWB[12];
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};
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/** @brief HW implements 11 Host-to-Target VW registers as an array */
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struct espi_msvw_ar_regs {
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struct espi_msvw_reg MSVW[11];
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};
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/** @brief HW implements 11 Host-to-Target VW registers as named registers */
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struct espi_msvw_named_regs {
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struct espi_msvw_reg MSVW00;
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struct espi_msvw_reg MSVW01;
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struct espi_msvw_reg MSVW02;
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struct espi_msvw_reg MSVW03;
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struct espi_msvw_reg MSVW04;
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struct espi_msvw_reg MSVW05;
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struct espi_msvw_reg MSVW06;
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struct espi_msvw_reg MSVW07;
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struct espi_msvw_reg MSVW08;
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struct espi_msvw_reg MSVW09;
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struct espi_msvw_reg MSVW10;
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};
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/** @brief eSPI M2S VW registers as an array of words at 0x400F9C00 */
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struct espi_msvw32_regs {
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volatile uint32_t MSVW32[11 * 3];
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};
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/** @brief eSPI 64-bit Target-to-Host Virtual Wire register */
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struct espi_smvw_reg {
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volatile uint8_t INDEX;
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volatile uint8_t STOM;
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volatile uint8_t SRC_CHG;
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uint8_t RSVD1[1];
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volatile uint32_t SRC;
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};
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/** @brief eSPI 64-bit Target-to-Host Virtual Wire register as bytes */
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struct espi_smvwb_reg {
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volatile uint8_t THVWB[8];
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};
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/** @brief HW implements 11 Target-to-Host VW registers as an array */
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struct espi_smvw_ar_regs {
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struct espi_smvw_reg SMVW[11];
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};
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/** @brief HW implements 11 Target-to-Host VW registers as named registers */
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struct espi_smvw_named_regs {
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struct espi_smvw_reg SMVW00;
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struct espi_smvw_reg SMVW01;
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struct espi_smvw_reg SMVW02;
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struct espi_smvw_reg SMVW03;
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struct espi_smvw_reg SMVW04;
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struct espi_smvw_reg SMVW05;
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struct espi_smvw_reg SMVW06;
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struct espi_smvw_reg SMVW07;
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struct espi_smvw_reg SMVW08;
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struct espi_smvw_reg SMVW09;
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struct espi_smvw_reg SMVW10;
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};
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/** @brief eSPI S2M VW registers as an array of words at 0x400F9E00 */
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struct espi_smvw32_regs {
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volatile uint32_t SMVW[11 * 2];
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* #ifndef _MEC172X_ESPI_VW_H */
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