85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_WDT_H
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#define _MEC_WDT_H
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#include <stdint.h>
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#include <stddef.h>
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/* Load register */
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#define MCHP_WDT_LOAD_REG_OFS 0x00u
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#define MCHP_WDT_LOAD_REG_MASK 0xffffu
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/* Control register */
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#define MCHP_WDT_CTRL_REG_OFS 0x04u
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#define MCHP_WDT_CTRL_REG_MASK 0x021du
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#define MCHP_WDT_CTRL_EN_POS 0u
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#define MCHP_WDT_CTRL_EN_MASK BIT(MCHP_WDT_CTRL_EN_POS)
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#define MCHP_WDT_CTRL_EN BIT(MCHP_WDT_CTRL_EN_POS)
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#define MCHP_WDT_CTRL_HTMR_STALL_POS 2u
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#define MCHP_WDT_CTRL_HTMR_STALL_MASK BIT(MCHP_WDT_CTRL_HTMR_STALL_POS)
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#define MCHP_WDT_CTRL_HTMR_STALL_EN BIT(MCHP_WDT_CTRL_HTMR_STALL_POS)
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#define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u
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#define MCHP_WDT_CTRL_WKTMR_STALL_MASK BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS)
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#define MCHP_WDT_CTRL_WKTMR_STALL_EN BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS)
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#define MCHP_WDT_CTRL_JTAG_STALL_POS 4u
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#define MCHP_WDT_CTRL_JTAG_STALL_MASK BIT(MCHP_WDT_CTRL_JTAG_STALL_POS)
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#define MCHP_WDT_CTRL_JTAG_STALL_EN BIT(MCHP_WDT_CTRL_JTAG_STALL_POS)
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/*
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* WDT mode selecting action taken upon count expiration.
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* 0 = Generate chip reset
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* 1 = Clear this bit,
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* Set event status
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* Generate interrupt if event IEN bit is set
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* Kick WDT causing it to reload from LOAD register
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* If interrupt is enabled in GIRQ21 and NVIC then the EC will jump
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* to the WDT ISR.
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*/
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#define MCHP_WDT_CTRL_MODE_POS 9u
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#define MCHP_WDT_CTRL_MODE_MASK BIT(MCHP_WDT_CTRL_MODE_POS)
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#define MCHP_WDT_CTRL_MODE_RESET 0u
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#define MCHP_WDT_CTRL_MODE_IRQ BIT(MCHP_WDT_CTRL_MODE_POS)
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/* WDT Kick register. Write any value to reload counter */
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#define MCHP_WDT_KICK_REG_OFS 0x08u
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#define MCHP_WDT_KICK_REG_MASK 0xffu
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#define MCHP_WDT_KICK_VAL 0
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/* WDT Count register. Read only */
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#define MCHP_WDT_CNT_RO_REG_OFS 0x0cu
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#define MCHP_WDT_CNT_RO_REG_MASK 0xffffu
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/* Status Register */
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#define MCHP_WDT_STS_REG_OFS 0x10u
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#define MCHP_WDT_STS_REG_MASK 0x01u
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#define MCHP_WDT_STS_EVENT_IRQ_POS 0u
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#define MCHP_WDT_STS_EVENT_IRQ BIT(MCHP_WDT_STS_EVENT_IRQ_POS)
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/* Interrupt Enable Register */
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#define MCHP_WDT_IEN_REG_OFS 0x14u
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#define MCHP_WDT_IEN_REG_MASK 0x01u
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#define MCHP_WDT_IEN_EVENT_IRQ_POS 0u
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#define MCHP_WDT_IEN_EVENT_IRQ_MASK BIT(MCHP_WDT_IEN_EVENT_IRQ_POS)
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#define MCHP_WDT_IEN_EVENT_IRQ_EN BIT(MCHP_WDT_IEN_EVENT_IRQ_POS)
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/** @brief Watchdog timer. Size = 24(0x18) */
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struct wdt_regs {
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volatile uint16_t LOAD;
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uint8_t RSVD1[2];
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volatile uint16_t CTRL;
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uint8_t RSVD2[2];
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volatile uint8_t KICK;
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uint8_t RSVD3[3];
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volatile uint16_t CNT;
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uint8_t RSVD4[2];
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volatile uint16_t STS;
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uint8_t RSVD5[2];
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volatile uint8_t IEN;
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};
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#endif /* #ifndef _MEC_WDT_H */
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